|
|
PDF XCR3512XL Data sheet ( Hoja de datos )
| Número de pieza | XCR3512XL | |
| Descripción | 512 Macrocell CPLD | |
| Fabricantes | Xilinx | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de XCR3512XL (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
|
No Preview Available !
0
R XCR3512XL: 512 Macrocell CPLD
DS081 (v1.2) September 4, 2001
0 14 Advance Product Specification
Features
• Lowest power 512 macrocell CPLD
• 7.5 ns pin-to-pin logic delays
• System frequencies up to 127 MHz
• 512 macrocells with 12,800 usable gates
• Available in small footprint packages
- 208-pin PQFP (180 user I/O)
- 256-ball FBGA (212 user I/O)
- 324-ball FBGA (260 user I/O)
• Optimized for 3.3V systems
- Ultra low power operation
- 5V tolerant I/O pins with 3.3V core supply
- Advanced 0.35 micron five layer metal EEPROM
process
- FZP™ CMOS design technology
• Advanced system features
- In-system programming
- Input registers
- Predictable timing model
- Up to 23 clocks available per function block
- Excellent pin retention during design changes
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
- Four global clocks
- Eight product term control terms per function block
• Fast ISP programming times
• Port Enable pin for additional I/O
ww•w.D2at.a7SVheteot43U..6coVmsupply voltage at industrial grade voltage
range
• Programmable slew rate control per output
• Security bit prevents unauthorized access
• Refer to XPLA3 family data sheet (DS012) for
architecture description
Description
The XCR3512XL is a 3.3V, 512 macrocell CPLD targeted at
power sensitive designs that require leading edge program-
mable logic solutions. A total of 32 function blocks provide
12,800 usable gates. Pin-to-pin propagation delays are
7.5 ns with a maximum system frequency of 127 MHz.
TotalCMOS™ Design Technique for
Fast Zero Power
Xilinx offers a TotalCMOS CPLD, both in process technol-
ogy and design technique. Xilinx employs a cascade of
CMOS gates to implement its sum of products instead of
the traditional sense amp approach. This CMOS gate imple-
mentation allows Xilinx to offer CPLDs that are both high
performance and low power, breaking the paradigm that to
have low power, you must have low performance. Refer to
Figure 1 and Table 1 showing the ICC vs. Frequency of our
XCR3512XL TotalCMOS CPLD (data taken with 32
up/down, loadable 16-bit counters at 3.3V, 25°C).
140
120
100
80
60
40
20
0
0
20 40 60 80 100 120 140 160
Frequency (MHz)
DS024_01_112700
Figure 1: XCR3512XL Typical ICC vs. Frequency at VCC
= 3.3V, 25°C
Table 1: Typical ICC vs. Frequency at VCC = 3.3V, 25°C
Frequency (MHz)
0
1 10 20
Typical ICC (mA)
TBD TBD TBD TBD
40
TBD
60
TBD
80
TBD
100
TBD
120
TBD
140
TBD
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS081 (v1.2) September 4, 2001
Advance Product Specification
www.xilinx.com
1-800-255-7778
1
1 page  
R
Switching Characteristics
VCC
S1
R1
VIN
R2
VOUT
C1
S2
XCR3512XL: 512 Macrocell CPLD
Component
R1
R2
C1
Values
390Ω
390Ω
35 pF
Measurement
S1
TPOE (High)
TPOE (Low)
TP
Open
Closed
Closed
Note: For TPOD, C1 = 5 pF
S2
Closed
Open
Closed
Figure 3: AC Load Circuit
DS013_03_050200
7.5
7.4
7.3
7.2
7.1
7.0
6.9
www.Da6ta.8Sheet4U.com
6.7
6.6
6.5
6.4
6.3
1 2 4 8 16
Number of Adjacent Outputs Switching
DS024_04_11800
Figure 4: Derating Curve for TPD2
+3.0V
90%
10%
0V
TR
1.5 ns
TL
1.5 ns
Measurements:
All circuit delays are measured at the +1.5V level of
inputs and outputs, unless otherwise specified.
DS017_05_042800
Figure 5: Voltage Waveform
DS081 (v1.2) September 4, 2001
Advance Product Specification
www.xilinx.com
1-800-255-7778
5
5 Page 
R XCR3512XL: 512 Macrocell CPLD
Table 3: XCR3512XL I/O Pins (Continued)
Function
Block Macrocell PQ208
FT256
22 9
--
22 10 - -
22 11 - -
22 12 - -
22 13 - -
22 14 139 G4
22 15
- G1
22 16 138 G3
23 1 173 D7
23 2
- B7
23 3 175 C7
23 4
- C8
23 5
--
23 6
--
23 7
--
23 8
--
23 9
--
23 10 - -
23 11 - -
23 12 - -
23 13
www.Da2ta3Sheet4U.com14
-
176(1)
-
A7(1)
23 15 177 D8
23 16 178 B8
24 1 137 H1
24 2 136 H4
24 3 135 G2
24 4
- H3
24 5
--
24 6
--
24 7
--
24 8
--
24 9
--
24 10 - -
24 11 - -
FG324
-
-
-
-
H1
J4
J3
J2
A9
D10
C10
B10
-
-
-
-
-
-
-
-
A10
D11(1)
C11
B11
J1
K4
K3
K2
-
-
-
-
-
-
-
Table 3: XCR3512XL I/O Pins (Continued)
Function
Block Macrocell PQ208
FT256
24 12 - -
24 13 133 J1
24 14 - -
24 15 - -
24 16 132 J3
25 1 105 P2
25 2 106 P3
25 3
--
25 4 108 T1
25 5
--
25 6
--
25 7
--
25 8
--
25 9
--
25 10 - -
25 11 - -
25 12 - -
25 13 - -
25 14 109 N3
25 15 110 R1
25 16 111 M4
26 1 104 M5
26 2
- N4
26 3 103 R2
26 4
- T2
26 5
--
26 6
--
26 7
--
26 8
--
26 9
--
26 10 - -
26 11 - -
26 12 - -
26 13 102 P4
26 14 - -
FG324
-
K1
L1
L4
L3
AA1
Y3
Y2
W3
-
-
-
-
-
-
-
-
Y1
W2
W1
V3
AB1
AA2
AB2
AA3
-
-
-
-
-
-
-
-
Y4
AB3
DS081 (v1.2) September 4, 2001
Advance Product Specification
www.xilinx.com
1-800-255-7778
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet XCR3512XL.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| XCR3512XL | 512 Macrocell CPLD | Xilinx |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |