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PDF 74AVC16T245 Data sheet ( Hoja de datos )
| Número de pieza | 74AVC16T245 | |
| Descripción | 16-bit Dual Supply Translating Transceiver | |
| Fabricantes | NXP Semiconductors | |
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74AVC16T245
16-bit dual supply translating transceiver with configurable
voltage translation; 3-state
Rev. 01 — 1 October 2009
Product data sheet
1. General description
The 74AVC16T245 is a 16-bit transceiver with bidirectional level voltage translation and
3-state outputs.The device can be used as two 8-bit transceivers or as a 16-bit
transceiver. It has dual supplies (VCC(A) and VCC(B)) for voltage translation and two 8-bit
input-output ports (nAn and nBn) each with its own output enable (nOE) and send/receive
(nDIR) input for direction control. VCC(A) and VCC(B) can be independently supplied at any
voltage between 0.8 V and 3.6 V making the device suitable for low voltage translation
between any of the following voltages: 0.8 V,1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V. A HIGH on
nDIR selects transmission from nAn to nBn while a LOW on nDIR selects transmission
from nBn to nAn. A HIGH on nOE causes the outputs to assume a high-impedance
OFF-state
The device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing any damaging backflow current through the
device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at
GND level, both nAn and nBn are in the high-impedance OFF-state.
2. Features
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I Wide supply voltage range:
N VCC(A): 0.8 V to 3.6 V
N VCC(B): 0.8 V to 3.6 V
I Complies with JEDEC standards:
N JESD8-12 (0.8 V to 1.3 V)
N JESD8-11 (0.9 V to 1.65 V)
N JESD8-7 (1.2 V to 1.95 V)
N JESD8-5 (1.8 V to 2.7 V)
N JESD8-B (2.7 V to 3.6 V)
I ESD protection:
N HBM JESD22-A114E Class 3B exceeds 8000 V
N MM JESD22-A115-A exceeds 200 V
N CDM JESD22-C101C exceeds 1000 V
I Maximum data rates:
N 380 Mbit/s (≥ 1.8 V to 3.3 V translation)
N 200 Mbit/s (≥ 1.1 V to 3.3 V translation)
N 200 Mbit/s (≥ 1.1 V to 2.5 V translation)
N 200 Mbit/s (≥ 1.1 V to 1.8 V translation)
N 150 Mbit/s (≥ 1.1 V to 1.5 V translation)
1 page  
NXP Semiconductors
74AVC16T245
16-bit dual supply translating transceiver; 3-state
terminal 1
index area
D1 A32 A31 A30 A29 A28 A27 D4
A1 D5
B20 B19 B18
D8 A26
A2
B1
A3
B2
A4
B3
A5
B4
A6
B5
A7
B6
A8
B7
A9
A10 D6
74AVC16T245
GND(1)
B8 B9 B10
A25
B17
A24
B16
A23
B15
A22
B14
A21
B13
A20
B12
A19
B11
A18
D7 A17
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D2 A11 A12 A13 A14 A15 A16 D3
Transparent top view
001aak429
(1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input.
Fig 5. Pin configuration SOT1025-1 (HUQFN60U)
74AVC16T245_1
Product data sheet
Rev. 01 — 1 October 2009
© NXP B.V. 2009. All rights reserved.
5 of 27
5 Page 
NXP Semiconductors
74AVC16T245
16-bit dual supply translating transceiver; 3-state
Table 8.
VCC(A)
0V
0.8 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
Typical total supply current (ICC(A) + ICC(B))
VCC(B)
0V
0.8 V
1.2 V
1.5 V
0 0.1 0.1 0.1
0.1 0.1 0.1 0.1
0.1 0.1 0.1 0.1
0.1 0.1 0.1 0.1
0.1 0.1 0.1 0.1
0.1 0.3 0.1 0.1
0.1 1.6 0.8 0.4
10. Dynamic characteristics
1.8 V
0.1
0.1
0.1
0.1
0.1
0.1
0.2
2.5 V
0.1
0.3
0.1
0.1
0.1
0.1
0.1
3.3 V
0.1
1.6
0.8
0.4
0.2
0.1
0.1
Unit
µA
µA
µA
µA
µA
µA
µA
Table 9. Typical power dissipation capacitance at VCC(A) = VCC(B) and Tamb = 25 °C [1][2]
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
VCC(A) = VCC(B)
0.8 V 1.2 V 1.5 V 1.8 V
CPD power dissipation A port: (direction A to B); 0.2 0.2 0.2 0.2
capacitance
output enabled
A port: (direction A to B); 0.2 0.2 0.2 0.2
output disabled
A port: (direction B to A);
output enabled
9
9.7 9.8 10.3
A port: (direction B to A); 0.6 0.6 0.6 0.7
output disabled
B port: (direction A to B);
output enabled
9
9.7 9.8 10.3
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B port: (direction A to B); 0.6 0.6 0.6 0.7
output disabled
B port: (direction B to A); 0.2 0.2 0.2 0.2
output enabled
B port: (direction B to A); 0.2 0.2 0.2 0.2
output disabled
[1] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of the outputs.
[2] fi = 10 MHz; VI = GND to VCC; tr = tf = 1 ns; CL = 0 pF; RL = ∞ Ω.
2.5 V
0.3
0.3
11.7
0.7
11.7
0.7
0.3
0.3
3.3 V
0.4
Unit
pF
0.4 pF
13.7 pF
0.7 pF
13.7 pF
0.7 pF
0.4 pF
0.4 pF
74AVC16T245_1
Product data sheet
Rev. 01 — 1 October 2009
© NXP B.V. 2009. All rights reserved.
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