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PDF UPD161644 Data sheet ( Hoja de datos )
| Número de pieza | UPD161644 | |
| Descripción | 241 OUTPUT GATE DRIVER | |
| Fabricantes | NEC | |
| Logotipo |  |
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PRELIMINARY PRODUCT INFORMATION
MOS INTEGRATED CIRCUIT
µPD161644
241 OUTPUT GATE DRIVER WITH POWER SUPPLY FOR TFT-LCD GATE DRIVER
DESCRIPTION
The µPD161644 is a TFT-LCD gate driver with power supply for TFT-LCD driver. Because this gate driver has a
level shift circuit for logic input, it can output a high gate scanning voltage in response to a CMOS-level input. This
ICs can generate the levels which TFT-LCD driver need, from 2.7 V.
FEATURES
• High breakdown voltage output (VDD1-VSS3 = 40 V MAX.)
• 2.7 V CMOS level input
• Number of output: 241 output selectable
• To generate 4 levels from single voltage input
• To integrate regulator circuit for source driver
• Mode setting from source driver: Serial I/F or pin control
• On-chip VCOM driver
• On-chip gate output low-level selector
ORDERING INFORMATION
Part number
www.DataSheet4U.com µPD161644P
Package
Chip
Remark Purchasing the above chip entails the exchange of documents such as a separate memorandum or
product quality, so please contact one of our sales representatives.
The information contained in this document is being issued in advance of the production cycle for the
device. The parameters for the device may change before final production or NEC Corporation, at its own
discretion, may withdraw the device prior to its production.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S15797EJ1V4PM00 (1st edition)
Date Published October 2002 NS CP(K)
Printed in Japan
The mark ! shows major revised points.
©
2001
1 page  
µPD161644
1.5 Variable Boost Steps
The boost steps of VDD1, VSS2, VSS3 are selected according to how the external capacitor is connected.
The examples of connection are shown below. VS is selected as a boost reference voltage in these examples (short
between the VS and VGD pins).
VDD2 = VDC x 3
C1+
C1−
VDD2
C2+
C2−
VDD2 = VDC x 2
(dual mode)
C1+
C1−
VDD2
C2+
C2−
VDD2 = VDC x 2
(single mode)
C1+
C1− VDD2
C2+
C2−
VDD1 = VGD x 3
VSS2 = VGD x −2
VSS3 = VGD x −3
C3+ VDD1
C3−
C4+ VSS2
C4−
C5+ VSS3
C5−
VDD1 = VGD x 3
VSS2 = −
VSS3 = VGD x −2
C3+
VDD1
C3−
C4+
VSS2
C4−
C5+
VSS3
C5−
VDD1 = VGD x 2
VSS2 = VGD x −1
VSS3 = VGD x −2
C3+
C3−
VDD1
C4+ VSS2
C4−
C5+ VSS3
C5−
VDD1 = VGD x 2
VSS2 = −
VSS3 = VGD x −1
C3+ VDD1
C3−
C4+ VSS2
C4−
C5+ VSS3
C5−
www.DataSheet4U.com
VSS4 = VDC x −1
C6+
C6−
VSS4
VSS4 = −
C6+ VSS4
C6−
Preliminary Product Information S15797EJ1V4PM
5
5 Page 
µPD161644
Symbol
VS
MVS
Pin Name
Positive power
output supply for
driver
External resistor
input
Pad No.
118 to 123
117
PVCC1
PVSS1
PVSS3
CLK
Pull-up voltage
Pull-down voltage
Pull-down voltage
Shift clock input
6, 24, 125
20, 27, 131
21
139
STVR,
STVL
Start pulse
input/output pin
136,
137
OE1 Enable input 140
OE2 Enable input
www.DataSheet4U.com
141
R,/L
Shift direction
25
control
FRM
DCCLK
Frame signal input 129
Clock input for
DC/DC converter
138
(2/5)
I/O Function
Output Positive power supply voltage output for source driver. The VS
output voltage can be changed by setting VSEL0 to VSEL2.
Input
−
−
−
Input
I/O
Input
Input
Input
Input
Input
Any output voltage can be set by connecting an external resistor.
<EXRV = 0> Leave open.
<EXRV = 1> Connect to external resistor.
Pull-up voltage for mode setting pin.
Pull-down voltage for mode setting pin.
Pull-down voltage for mode setting pin.
Shift clock input pin of the internal shift resistor. The contents of
internal shift resistor are shifted at the rising edge of CLK.
Connect to GCLK pin of source driver.
Input/output pin of the internal shift resistor.
Start pulse signal is read at the rising edge of shift clock CLK and a
scan signal is output from the driver output pin.
The valid level of the STVR/STVL pin is determined by the setting
of STVSEL.
When STVSEL = L, the pulse becomes low level at the falling
edge of the 240th shift clock CLK and high level at falling edge of
the 241st clock.
If the level selected by OE1SEL is input, the driver output is fixed to
low level (When OE1SEL = L the driver output is fixed to low level if
a low level is input). However, the shift resistor is not cleared. And,
output enable actuation is asynchronous in the clock.
Connect to GOE1 pin of source driver.
If the level selected by OE2SEL is input, the driver output is fixed to
high level (When OE2SEL = L the driver output is fixed to low level
if a high level is input). However, the shift resistor is not cleared.
And, output enable actuation is asynchronous in the clock.
Connect to GOE2 pin of source driver.
The shift direction control pin of shift register. The shift directions
of the shift registers are as follows.
R,/L = H (right shift): STVR input, O1 →O241, STVL output
R,/L = L (left shift) : STVL input, O241 → O1, STVR output
Input frame reverse signals.
Connect to GFRAME pin of source driver.
To input the external clock for the DC/DC converter.
This pin is valid only when CLS0 = 1 and CLS1 = 1. In other
settings, leave open.
Preliminary Product Information S15797EJ1V4PM
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet UPD161644.PDF ] | |
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