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PDF PCA9702 Data sheet ( Hoja de datos )
| Número de pieza | PCA9702 | |
| Descripción | (PCA9701 / PCA9702) 18 V tolerant SPI 16-bit/8-bit GPI | |
| Fabricantes | NXP Semiconductors | |
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PCA9701; PCA9702
18 V tolerant SPI 16-bit/8-bit GPI with INT
Rev. 03 — 3 December 2008
Product data sheet
1. General description
The PCA9701/PCA9702 are low power 18 V tolerant SPI General Purpose Input (GPI)
shift register designed to monitor the status of switch inputs. It generates an interrupt
when one or more of the switch inputs change state. The input level is recognized as a
HIGH when it is greater than 0.7 × VDD and as a LOW when it is less than 0.4 × VDD
(minimum threshold of 2 V at 5 V node). The PCA9701 can monitor up to 16 switch inputs
and the PCA9702 can monitor up to 8 switch inputs.
The falling edge of the CS pin samples the input port status and clears the interrupt. When
CS is LOW, the rising edge of the SCLK loads the shift register and shifts the value out of
the shift register. The serial input is sampled on the falling edge of SCLK.
Each of the input ports has a 18 V breakdown ESD protection circuit. When used with a
series resistor (minimum 100 kΩ), the input can connect to a 12 V battery and support
double battery, reverse battery, 27 V jump start and 40 V load dump conditions in
automotive applications. Higher voltages can be tolerated on the inputs depending on the
series resistor used to limit the input current.
With both the high breakdown voltage and high ESD, these devices are useful for both
automotive (AEC-Q100 qualification available) and mobile applications.
The PCA9703/PCA9704 are new pin compatible devices for the PCA9701/PCA9702
which have an interrupt masking feature allowing selected inputs to not generate
interrupts and provides higher ground offset of 0.55 × VDD (minimum of 2.5 V at 5 V node)
with minimum hysteresis of 0.05 × VDD (minimum of 225 mV at 5 V node).
www.D2a.taSheFeet4Ua.ctoumres
I 16 general purpose input ports (PCA9701) or 8 general purpose input ports
(PCA9702)
I 18 V tolerant input ports with 100 kΩ external series resistor
I Input LOW threshold 0.4 × VDD with minimum of 2 V at VDD = 4.5 V
I Open-drain interrupt output
I Interrupt enable pin (INT_EN) disables interrupt output
I VDD range: 2.5 V to 5.5 V
I IDD is very low 2.5 µA maximum
I SPI serial interface with speeds up to 5 MHz
I AEC-Q100 qualification available
I ESD protection exceeds 8 kV HBM per JESD22-A114, 350 V MM per AEC-Q100, and
1000 V CDM per JESD22-C101
I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
1 page  
NXP Semiconductors
PCA9701; PCA9702
18 V tolerant SPI 16-bit/8-bit GPI with INT
6.2 Pin description
Table 2.
Symbol
SDOUT
INT
INT_EN
Pin description
Pin
SO24, TSSOP24
1
2
3
HWQFN24 TSSOP16
22 1
23 2
24 3
Type
output
output
input
IN0 4
IN1 5
IN2 6
IN3 7
IN4 8
IN5 9
IN6 10
IN7 11
VSS 12
IN8 13
IN9 14
IN10
15
IN11
16
IN12
17
IN13
18
IN14
19
www.DIaNta1S5heet4U.c2o0m
CS 21
SCLK
22
SDIN
23
VDD
24
1 4 input
2 5 input
3 6 input
4 7 input
5 9 input
6 10 input
7 11 input
8 12 input
9[1] 8
ground
10 -
input
11 -
input
12 -
input
13 -
input
14 -
input
15 -
input
16 -
input
17 -
input
18 13 input
19 14 input
20 15 input
21 16 supply
Description
3-state serial data output; normally high-impedance
open-drain interrupt output (active LOW)
interrupt output enable
1 = interrupt is enabled
0 = interrupt is disabled and high-impedance
input port 0
input port 1
input port 2
input port 3
input port 4
input port 5
input port 6
input port 7
ground supply
input port 8
input port 9
input port 10
input port 11
input port 12
input port 13
input port 14
input port 15
chip select (active LOW)
serial input clock
serial data input (20 µA pull-down)
supply voltage
[1] HWQFN24 package die supply ground is connected to both VSS pin and exposed center pad. VSS pin must be connected to supply
ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be
soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias
need to be incorporated in the PCB in the thermal pad region.
PCA9701_PCA9702_3
Product data sheet
Rev. 03 — 3 December 2008
© NXP B.V. 2008. All rights reserved.
5 of 28
5 Page 
NXP Semiconductors
PCA9701; PCA9702
18 V tolerant SPI 16-bit/8-bit GPI with INT
8.2.1 SBC wake port extension with cyclic biasing
System Basis Chips (SBC) offer many functions needed for in-vehicle networking
solutions. Some of the features built into SBC are:
• Transceivers (HS-CAN, LIN 2.0)
• Scalable voltage regulators
• Watchdog timers; wake-up function
• Fail-safe function
For more information on SBC, refer to
http://www.nxp.com/index.html#/pip/pip=[pfp=53482]|pp=[t=pfp,i=53482].
8.2.1.1 UJA106x with PCA9701, standby
www.DataSheet4U.com
alternate
PVR100AD-B5V0
V3
UJA106x
IN0 INT
IN1 INT_EN
PCA9701
VDD
IN15
CS
SDIN
SDOUT
SCLK
VSS
WAKE
V1 GND
VCC
CSN
MOSI
µC
MISO
SCLK
GND
002aae016
Fig 9. UJA106x with PCA9701 with supplied µC (standby)
• PCA970x fits to SBC UJA106x and UJA107x family
• PCA970x can be powered by V1 of SBC
• Extends the SBC with 8/16 additional wake inputs
• µC can be set to stop-mode during standby to save ECU standby current. SBC with
GPI periodically monitors the wake inputs
– Cyclic bias via V3
– Very low system current consumption even with clamped switches
PCA9701_PCA9702_3
Product data sheet
Rev. 03 — 3 December 2008
© NXP B.V. 2008. All rights reserved.
11 of 28
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet PCA9702.PDF ] | |
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