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PDF H5PS1G63EFR Data sheet ( Hoja de datos )
| Número de pieza | H5PS1G63EFR | |
| Descripción | 1Gb DDR21 SDRAM | |
| Fabricantes | hynix | |
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H5PS1G63EFR
1Gb(64Mx16) DDR2 SDRAM
H5PS1G63EFR
www.DataSheet4U.com
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 1.1/ Oct. 2008
1
1 page  
H5PS1G63EFR
1. Description
1.1 Device Features & Ordering Information
1.1.1 Key Features
• VDD = 1.8 +/- 0.1V
• VDDQ = 1.8 +/- 0.1V
• All inputs and outputs are compatible with SSTL_18 interface
• 8 banks
• Fully differential clock inputs (CK, /CK) operation
• Double data rate interface
• Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS)
• Differential Data Strobe (DQS, DQS)
• Data outputs on DQS, DQS edges when read (edged DQ)
• Data inputs on DQS centers when write(centered DQ)
• On chip DLL align DQ, DQS and DQS transition with CK transition
• DM mask write data-in at the both rising and falling edges of the data strobe
• All addresses and control inputs except data, data strobes and data masks latched on the rising
edges of the clock
• Programmable CAS latency 3,4, 5, 6 and 7 supported
• Programmable additive latency 0, 1, 2, 3, 4 and 5 supported
• Programmable burst length 4/8 with both nibble sequential and interleave mode
• Internal eight bank operations with single pulsed RAS
• Auto refresh and self refresh supported
• tRAS lockout supported
• 8K refresh cycles /64ms
• JEDEC standard 84ball FBGA(x16)
• Full strength driver option controlled by EMR
• On Die Termination supported
www.DataSheet4•U.cOofmf Chip Driver Impedance Adjustment supported
• Read Data Strobe supported (x8 only)
• Self-Refresh High Temperature Entry
• Average Refresh Period 7.8us at lower than Tcase 85°C, 3.9us at 85°C<Tcase<95°C
1.1.2 Ordering Information
Part No.
H5PS1G63EFR-20L
H5PS1G63EFR-25C
Power Supply
Clock
Frequency
VDD/VDDQ=1.8V
500Mhz
400Mhz
Max Data Rate
1000Mbps/pin
800Mbps/pin
Interface
SSTL_18
Package
84Ball FBGA
Note) Above Hynix P/N’s are Lead-free, RoHS Compliant and Halogen-free.
Rev. 1.1/Oct. 2008
5
5 Page 
H5PS1G63EFR
2.2.2.1 DDR2 SDRAM Mode Register Set (MRS)
The mode register stores the data for controlling the various operating modes of DDR2 SDRAM. It controls
CAS latency, burst length, burst sequence, test mode, DLL reset, tWR and various vendor specific options
to make DDR2 SDRAM useful for various applications. The default value of the mode register is not
defined, therefore the mode register must be written after power-up for proper operation. The mode regis-
ter is written by asserting low on CS, RAS, CAS, WE, BA0 and BA1, while controlling the state of address
pins A0 ~ A12. The DDR2 SDRAM should be in all bank precharge with CKE already high prior to writing
into the mode register. The mode register set command cycle time (tMRD) is required to complete the write
operation to the mode register. The mode register contents can be changed using the same command and
clock cycle requirements during normal operation as long as all banks are in the precharge state. The
mode register is divided into various fields depending on functionality. Burst length is defined by A0 ~ A2
with options of 4 and 8 bit burst lengths. The burst length decodes are compatible with DDR SDRAM. Burst
address sequence type is defined by A3, CAS latency is defined by A4 ~ A6. The DDR2 doesn’t support
half clock latency mode. A7 is used for test mode. A8 is used for DLL reset. A7 must be set to low for nor-
mal MRS operation. Write recovery time tWR is defined by A9 ~ A11. Refer to the table for specific codes.
Address Field BA2 BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Extended 0 0 0 PD
WR
DLL TM
/CAS Latency
BT
Burst Length
Mode Register
A8 DLL Reset
0 No
1 Yes
A7 mode
0 Normal
1 Test
A3 Burst Type Burst Length
0 Sequential
A2 A1 A0 BL
1 Interleave
010 4
011 8
A12
Active power
down exit time
0 Fast exit(use tXARD)
www.DataSheet4U.c1om Slow exit(use tXARDS)
Write recovery for autoprecharge
A11 A10 A9 WR(cycles)*1
0 00
Reserved
0 01
2
0 10
BA1 BA0
MRS mode
0 11
00
MRS
1 00
01
EMRS(1)
1 01
10
EMRS(2)
1 10
1 1 EMRS(3): Reserved
1 11
3
4
5
6
7
Reserved
MRS Default setting
Active Power donw exit
Fast Exit
WR
WR=4
/CAS Latency
CL=4
BT
Seq.
CAS Latency
A6 A5 A4 Latency
0 0 0 Reserved
0 0 1 Reserved
0 1 0 Reserved
0 11
3
1 00
4
1 01
5
1 10
6
1 11
7
Burst Length
BL=4
*1: WR(write recovery for autoprecharge) min is determined by tCK max and WR max is determined by tCK min.
WR in clock cycles is calculated by dividing tWR (in ns) by tCK (in ns) and rounding up to the next integer
(WR[cycles] = tWR(ns)/tCK(ns)). The mode register must be programmed to this value. This is also used with
tRP to determine tDAL.
Rev. 1.1/ Oct. 2008
11
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