PDF HYB18T512400BF Data sheet ( Hoja de datos )

Número de pieza	HYB18T512400BF
Descripción	512-Mbit Double-Data-Rate-Two SDRAM
Fabricantes	Qimonda
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No Preview Available ! HYB18T512400B[C/F] HYB18T512800B[C/F] HYB18T512160B[C/F] 512-Mbit Double-Data-Rate-Two SDRAM DDR2 SDRAM RoHS Compliant Products May 2007 www.DataSheet4U.com Internet Data Sheet Rev. 1.1 1 page Internet Data Sheet HYB18T512[40/80/16]0B[C/F] 512-Mbit Double-Data-Rate-Two SDRAM 1.2 Description The 512-Mb DDR2 DRAM is a high-speed Double-Data- Rate-Two CMOS DRAM device containing 536,870,912 bits and is internally configured as an quad-bank DRAM. The 512-Mb device is organized as either 32 Mbit × 4 I/O ×4 banks, 16 Mbit ×8 I/O × 4 banks or 8 Mbit ×16 I/O ×4 banks chip. These devices achieve high speed transfer rates starting at 400 Mb/sec/pin for general applications. See Table 1 for performance figures. The device is designed to comply with all DDR2 DRAM key features: 1. Posted CAS with additive latency 2. Write latency = read latency - 1 3. Normal and weak strength data-output driver 4. Off-Chip Driver (OCD) impedance adjustment 5. On-Die Termination (ODT) function All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a single ended DQS or differential DQS-DQS pair in a source synchronous fashion. A 16-bit address bus for ×4 and ×8 organized components and a 15-bit address bus for ×16 components is used to convey row, column and bank address information in a RAS- CAS multiplexing style. The DDR2 device operates with a 1.8 V ± 0.1 V power supply. An Auto-Refresh and Self-Refresh mode is provided along with various power-saving power-down modes. The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation. The DDR2 SDRAM is available in FBGA package. www.DataSheet4U.com Rev. 1.1, 2007-05 03292006-YBYM-WG0Z 5 5 Page Internet Data Sheet HYB18T512[40/80/16]0B[C/F] 512-Mbit Double-Data-Rate-Two SDRAM Ball# Name Ball Type Buffer Type A1 A7, B2, B8, D2, D8 VDD VSSQ PWR PWR — — A3, E3 VSS PWR — Power Supplies ×4/×8 organizations E2 VREF AI E1 VDDL PWR E9, H9, L1 VDD PWR E7 VSSDL PWR J1, K9 VSS PWR Power Supplies ×16 organization — — — — — J2 E9, G1, G3, G7, G9 VREF VDDQ AI PWR — — J1 E1, J9, M9, R1 E7, F2, F8, H2, H8 VDDL VDD VSSQ PWR PWR PWR — — — J7 A3, E3, J3, N1, P9 VSSDL VSS PWR PWR — — Not Connected ×4/×8 organization G1, L3,L7, L8 NC NC — Not Connected www.DataSheet4U.com ×4 organization A2, B1, B9, D1, NC NC D9 — Not Connected ×16 organization A2, E2, L1, R3, NC R7, R8 NC — Other Balls ×4/×8 organizations F9 ODT I SSTL Other Balls ×16 organization K9 ODT I SSTL Function Power Supply I/O Driver Power Supply Power Supply I/O Reference Voltage Power Supply Power Supply Power Supply Power Supply I/O Reference Voltage I/O Driver Power Supply Power Supply Power Supply I/O Driver Power Supply Power Supply Power Supply Not Connected Not Connected Not Connected On-Die Termination Control On-Die Termination Control Rev. 1.1, 2007-05 03292006-YBYM-WG0Z 11 11 Page

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