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PDF LY61L1288 Data sheet ( Hoja de datos )
| Número de pieza | LY61L1288 | |
| Descripción | 128K X 8 BIT HIGH SPEED CMOS SRAM | |
| Fabricantes | Lyontek | |
| Logotipo |  |
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®
Rev. 1.2
LY61L1288
128K X 8 BIT HIGH SPEED CMOS SRAM
REVISION HISTORY
Revision
Rev. 1.0
Rev. 1.1
Rev. 1.2
Description
Initial Issue
Delete Icc1 Spec.
Added I Grade Spec.
Revised Test Condition of ICC/ISB1/IDR
Revised VTERM to VT1 and VT2
Revised FEATURES & ORDERING INFORMATION
Lead free and green package available to Green package
available
Deleted TSOLDER in ABSOLUTE MAXIMUN RATINGS
Added packing type in ORDERING INFORMATION
Issue Date
Jul.25.2004
Sep.21.2004
Apr.20.2009
www.DataSheet4U.com
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
0
1 page  
®
Rev. 1.2
LY61L1288
128K X 8 BIT HIGH SPEED CMOS SRAM
CAPACITANCE (TA = 25℃, f = 1.0MHz)
PARAMETER
SYMBOL
MIN.
Input Capacitance
CIN -
Input/Output Capacitance
CI/O
-
Note : These parameters are guaranteed by device characterization, but not production tested.
MAX
6
8
UNIT
pF
pF
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0.2V to VCC - 0.2V
3ns
1.5V
CL = 30pF + 1TTL, IOH/IOL = -4mA/8mA
AC ELECTRICAL CHARACTERISTICS
(1) READ CYCLE
PARAMETER
SYM.
Read Cycle Time
tRC
Address Access Time
tAA
Chip Enable Access Time
tACE
Output Enable Access Time
tOE
Chip Enable to Output in Low-Z tCLZ*
Output Enable to Output in Low-Z tOLZ*
Chip Disable to Output in High-Z tCHZ*
Output Disable to Output in High-Z tOHZ*
Output Hold from Address Change tOH
LY61L1288
-8
MIN. MAX.
8-
-8
-8
-4
2-
0-
-4
-4
3-
LY61L1288
-10
MIN. MAX.
10 -
- 10
- 10
-5
2-
0-
-5
-5
3-
LY61L1288
-12
MIN. MAX.
12 -
- 12
- 12
-6
3-
0-
-6
-6
3-
LY61L1288 UNIT
-15
MIN. MAX.
15 - ns
- 15 ns
- 15 ns
- 7 ns
4 - ns
0 - ns
- 7 ns
- 7 ns
3 - ns
www.Da(t2aS) hWeeRt4IUT.EcoCmYCLE
PARAMETER
SYM. LY61L1288 LY61L1288
-8 -10
MIN. MAX. MIN. MAX.
Write Cycle Time
tWC 8 - 10 -
Address Valid to End of Write tAW 6.5 - 8 -
Chip Enable to End of Write
tCW 6.5 - 8 -
Address Set-up Time
tAS 0 - 0 -
Write Pulse Width
tWP 6.5 - 8 -
Write Recovery Time
tWR 0 - 0 -
Data to Write Time Overlap
tDW 5 - 6 -
Data Hold from End of Write Time tDH
0-0-
Output Active from End of Write tOW* 1.5 - 2 -
Write to Output in High-Z
tWHZ*
-
5
-
6
*These parameters are guaranteed by device characterization, but not production tested.
LY61L1288
-12
MIN. MAX.
12 -
10 -
10 -
0-
9-
0-
7-
0-
3-
-7
LY61L1288
-15
MIN. MAX.
15 -
12 -
12 -
0-
10 -
0-
8-
0-
4-
-8
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
4
5 Page 
®
Rev. 1.2
LY61L1288
128K X 8 BIT HIGH SPEED CMOS SRAM
THIS PAGE IS LEFT BLANK INTENTIONALLY.
www.DataSheet4U.com
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
10
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet LY61L1288.PDF ] | |
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