PDF LY62L25716 Data sheet ( Hoja de datos )

Número de pieza	LY62L25716
Descripción	256K X 16 BIT LOW POWER CMOS SRAM
Fabricantes	Lyontek
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No Preview Available ! ® Rev. 2.4 LY62L25716 256K X 16 BIT LOW POWER CMOS SRAM REVISION HISTORY Revision Rev. 1.0 Rev. 2.0 Rev. 2.1 Rev. 2.2 Rev. 2.3 Rev. 2.4 Description Initial Issue Revised ISB(max) : 0.5mA => 1.25mA Adding 44-pin TSOP-II Adding 48-ball BGA Revised IDR Deleted L Spec. Added SL Spec. Revised Test Condition of ICC/ISB1/IDR Revised VTERM to VT1 and VT2 Added ISB1/IDR values when TA = 25℃ and TA = 40℃ Revised FEATURES & ORDERING INFORMATION Lead free and green package available to Green package available Added packing type in ORDERING INFORMATION Deleted TSOLDER in ABSOLUTE MAXIMUN RATINGS Issue Date Apr.19.2006 May.11.2006 Jul.5.2006 Dec.20.2006 Mar.3.2008 Mar.30.2009 www.DataSheet4U.com Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 0 1 page ® Rev. 2.4 LY62L25716 256K X 16 BIT LOW POWER CMOS SRAM ABSOLUTE MAXIMUN RATINGS* PARAMETER SYMBOL RATING UNIT Voltage on VCC relative to VSS VT1 -0.5 to 4.6 V Voltage on any other pin relative to VSS VT2 -0.5 to VCC+0.5 V Operating Temperature 0 to 70(C grade) TA -20 to 80(E grade) ℃ Storage Temperature TSTG -40 to 85(I grade) -65 to 150 ℃ Power Dissipation PD 1 W DC Output Current IOUT 50 mA Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. TRUTH TABLE MODE CE# CE2 OE# Standby HX XL XX Output Disable L L H H LH Read LH LH www.DaWtaSrihteeet4U.com LH LH LH Note: H = VIH, L = VIL, X = Don't care. X X X H H L L L X X X WE# LB# XX XX XH HL HX HL HH HL LL LH LL UB# X X H X L H L L H L L I/O OPERATION DQ0-DQ7 DQ8-DQ15 High – Z High – Z High – Z High – Z High – Z High – Z High – Z High – Z High – Z High – Z DOUT High – Z DOUT DIN High – Z DIN High – Z DOUT DOUT High – Z DIN DIN SUPPLY CURRENT ISB,ISB1 ICC,ICC1 ICC,ICC1 ICC,ICC1 Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 4 5 Page ® Rev. 2.4 LY62L25716 256K X 16 BIT LOW POWER CMOS SRAM DATA RETENTION CHARACTERISTICS PARAMETER VCC for Data Retention Data Retention Current Chip Disable to Data Retention Time Recovery Time tRC = Read Cycle Time SYMBOL TEST CONDITION VDR CE# ≧ VCC - 0.2V or CE2 ≦ 0.2V LL LLE/LLI IDR VCC = 1.5V CE# ≧ VCC - 0.2V or CE2 ≦ 0.2V Other pins at 0.2V or VCC-0.2V SL SLE SLI 25℃ 40℃ SL SLE/SLI tCDR See Data Retention Waveforms (below) tR MIN. 1.5 - - - - - - 0 tRC* DATA RETENTION WAVEFORM Low Vcc Data Retention Waveform (1) (CE# controlled) TYP. - 1.0 1.0 0.5 0.5 0.5 0.5 - - MAX. 3.6 12 16 2.5 UNIT V µA µA µA 2.5 µA 8 µA 10 µA - ns - ns Vcc CE# Vcc(min.) tCDR VIH VDR ≧ 1.5V CE# ≧ Vcc-0.2V Vcc(min.) tR VIH Low Vcc Data Retention Waveform (2) (CE2 controlled) www.DataSheet4U.com Vcc CE2 Vcc(min.) tCDR VIL VDR ≧ 1.5V CE2 ≦ 0.2V Low Vcc Data Retention Waveform (3) (LB#, UB# controlled) Vcc LB#,UB# Vcc(min.) tCDR VIH VDR ≧ 1.5V LB#,UB# ≧ Vcc-0.2V Vcc(min.) tR VIL Vcc(min.) tR VIH Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 10 11 Page

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