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Número de pieza | LY62L12816 | |
Descripción | 128K X 16 BIT LOW POWER CMOS SRAM | |
Fabricantes | Lyontek | |
Logotipo | ||
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Rev. 1.2
LY62L12816
128K X 16 BIT LOW POWER CMOS SRAM
REVISION HISTORY
Revision
Rev. 1.0
Rev. 1.1
Rev. 1.2
Description
Initial Issue
Revised Package Outline Dimension(TSOP-II)
Added ISB1/IDR values when TA = 25℃ and TA = 40℃
Added SL grade
Deleted L grade
Revised FEATURES & ORDERING INFORMATION
Lead free and green package available to Green package
available
Added packing type in ORDERING INFORMATION
Revised VTERM to VT1 and VT2
Deleted TSOLDER in ABSOLUTE MAXIMUN RATINGS
Issue Date
Jul.25.2004
Apr.12.2007
Mar.30.2009
www.DataSheet4U.com
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
0
1 page ®
Rev. 1.2
LY62L12816
128K X 16 BIT LOW POWER CMOS SRAM
CAPACITANCE (TA = 25℃, f = 1.0MHz)
PARAMETER
SYMBOL
MIN.
Input Capacitance
CIN -
Input/Output Capacitance
CI/O
-
Note : These parameters are guaranteed by device characterization, but not production tested.
MAX
6
8
UNIT
pF
pF
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0.2V to VCC - 0.2V
3ns
1.5V
CL = 30pF + 1TTL, IOH/IOL = -1mA/2mA
AC ELECTRICAL CHARACTERISTICS
(1) READ CYCLE
PARAMETER
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low-Z
Output Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
LB#, UB# Access Time
LB#, UB# to High-Z Output
www.DaLtaBS#h,eeUt4BU#.ctoomLow-Z Output
SYM.
tRC
tAA
tACE
tOE
tCLZ*
tOLZ*
tCHZ*
tOHZ*
tOH
tBA
tBHZ*
tBLZ*
LY62L12816-45 LY62L12816-55 LY62L12816-70
MIN. MAX. MIN. MAX. MIN. MAX.
45 - 55 - 70 -
- 45 - 55 - 70
- 45 - 55 - 70
- 25 - 30 - 35
10 - 10 - 10 -
5-5-5-
- 15 - 20 - 25
- 15 - 20 - 25
10 - 10 - 10 -
- 45 - 55 - 70
- 20 - 25 - 30
10 - 10 - 10 -
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(2) WRITE CYCLE
PARAMETER
SYM. LY62L12816-45 LY62L12816-55 LY62L12816-70
MIN. MAX. MIN. MAX. MIN. MAX.
Write Cycle Time
tWC 45 - 55 - 70 -
Address Valid to End of Write tAW 40 - 50 - 60 -
Chip Enable to End of Write
tCW 40 - 50 - 60 -
Address Set-up Time
tAS 0 - 0 - 0 -
Write Pulse Width
tWP 35 - 45 - 55 -
Write Recovery Time
tWR 0 - 0 - 0 -
Data to Write Time Overlap
tDW 20 - 25 - 30 -
Data Hold from End of Write Time tDH
0-0-0-
Output Active from End of Write
tOW*
5
-
5
-
5
-
Write to Output in High-Z
tWHZ* - 15 - 20 - 25
LB#, UB# Valid to End of Write
tBW
35 - 45 - 60 -
*These parameters are guaranteed by device characterization, but not production tested.
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
4
5 Page ®
Rev. 1.2
LY62L12816
128K X 16 BIT LOW POWER CMOS SRAM
48-ball 6mm × 8mm TFBGA Package Outline Dimension
www.DataSheet4U.com
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
10
11 Page |
Páginas | Total 13 Páginas | |
PDF Descargar | [ Datasheet LY62L12816.PDF ] |
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