ZL6100 Datasheet PDF - Intersil Corporation
| Part Number | ZL6100 | |
| Description | Adaptive Digital DC/DC Controller | |
| Manufacturers | Intersil Corporation | |
| Logo |  |
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NORETCROEMCOMMENMDEENDDZRELDE6P1F0LO5ARCNEEMWENDTEPSAIDGRaNTtSa Sheet
August 29, 2012
ZL6100
FN6876.3
Adaptive Digital DC/DC Controller with
Drivers and Current Sharing
ZL6100 is a digital power controller with integrated MOSFET
drivers. Current sharing allows multiple devices to be
connected in parallel to source loads with very high current
demands. Adaptive performance optimization algorithms
improve power conversion efficiency across the entire load
range. Zilker Labs Digital-DC™ technology enables a blend
of power conversion performance and power management
features.
The ZL6100 is designed to be a flexible building block for DC
power and can be easily adapted to designs ranging from a
single-phase power supply operating from a 3.3V input to a
multi-phase supply operating from a 12V input. The ZL6100
eliminates the need for complicated power supply managers
as well as numerous external discrete components.
All operating features can be configured by simple
pin-strap/resistor selection or through the SMBus™ serial
interface. The ZL6100 uses the PMBus™ protocol for
communication with a host controller and the Digital-DC bus
for communication between other Zilker Labs devices.
Ordering Information
PART
NUMBER
PART
(Notes 1, 2, 3) MARKING
TEMP.
RANGE
(°C)
PACKAGE PKG.
(Pb-Free) DWG. #
ZL6100ALAF
(Note 4)
6100
-40 to +85 36 Ld QFN L36.6x6C
ZL6100ALBF 6100
-40 to +85 36 Ld QFN L36.6x6C
NOTES:
1. Add “T*” suffix for tape and reel. Please refer to TB347 for details
on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special
Pb-free material sets, molding compounds/die attach materials,
and 100% matte tin plate plus anneal (e3 termination finish, which
is RoHS compliant and compatible with both SnPb and Pb-free
soldering operations). Intersil Pb-free products are MSL classified
at Pb-free peak reflow temperatures that meet or exceed the Pb-
free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device
information page for ZL6100. For more information on
MSL, please see Technical Brief TB363.
4. Only for customers that do not want to order new
firmware.
Features
Power Conversion
• Efficient Synchronous Buck Controller
• Adaptive Light Load Efficiency Optimization
• 3V to 14V Input Range
• 0.54V to 5.5V Output Range (with Margin)
• ±1% Output Voltage Accuracy
• Internal 3A MOSFET Drivers
• Fast Load Transient Response
• Current Sharing and Phase Interleaving
• Snapshot™ Parameter Capture
• 36 Ld 6mmx6mm QFN Package
• Pb-Free (RoHS Compliant)
Power Management
• Digital Soft-start/stop
• Precision Delay and Ramp-up
• Power-Good/Enable
• Voltage Tracking, Sequencing and Margining
• Voltage/Current/Temperature Monitoring
• I2C/SMBus Interface (PMBus Compatible)
• Output Voltage and Current Protection
• Internal Non-volatile Memory (NVM)
Applications
• Servers/Storage Equipment
• Telecom/Datacom Equipment
• Power Supplies (Memory, DSP, ASIC, FPGA)
EN PG DLY FC ILIM CFG UVLO V25 VR VDD
V
SS
VTRK
MGN
SYNC
DDC
SCL
SDA
SALRT
POWER
MANAGEMENT
NON-
VOLATILE
MEMORY
I2 C
PWM
CONTROLLER
MONITOR
ADC
LDO
DRIVER
CURRENT
SENSE
TEMP
SENSOR
BST
GH
SW
GL
VSEN+
VSEN-
ISENA
ISENB
SA
XTEMP
PGND SGND DGND
FIGURE 1. BLOCK DIAGRAM
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
Copyright Intersil Americas Inc. 2009, 2010, 2012. All Rights Reserved
All other trademarks mentioned are the property of their respective owners
|
| |
 
ZL6100
Electrical Specifications VDD = 12V, TA = -40°C to +85°C, unless otherwise specified. Typical values are at TA = +25°C. Boldface limits
apply over the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
CONDITIONS
MIN MAX
(Note 19) TYP (Note 19) UNIT
UVLO Set-point Accuracy
-150 – 150 mV
UVLO Hysteresis
Factory default
– 3 –%
Configurable via I2C/SMBus
0 – 100 %
UVLO Delay
– – 2.5 µs
Power-Good VOUT Threshold
Power-Good VOUT Hysteresis
Power-Good Delay
Factory default
Factory default
Using pin-strap or resistor (Note 15)
– 90 – % VOUT
– 5 –%
0 – 200 ms
Configurable via I2C/SMBus
0 – 500 s
VSEN Undervoltage Threshold
VSEN Overvoltage Threshold
VSEN Undervoltage Hysteresis
VSEN Undervoltage/Overvoltage Fault
Response Time
Factory default
Configurable via I2C/SMBus
Factory default
Configurable via I2C/SMBus
Factory default
Configurable via I2C/SMBus
– 85 – % VOUT
0 – 110 % VOUT
– 115 – % VOUT
0 – 115 % VOUT
– 5 – % VOUT
– 16 – µs
5 – 60 µs
Current Limit Set-point Accuracy
(VOUT Referenced)
Current Limit Set-point Accuracy
(Ground referenced)
– ±10 – % FS
(Note 16)
– ±10 – % FS
(Note 16)
Current Limit Protection Delay
Factory default
– 5 – tSW
(Note 17)
Configurable via I2C/SMBus
1 – 32 tSW
(Note 17)
Temperature Compensation of
Current Limit Protection Threshold
Factory default
Configurable via I2C/SMBus
– 4400 – ppm/°C
100 – 12700 ppm/°C
Thermal Protection Threshold
(Junction Temperature)
Factory default
Configurable via I2C/SMBus
– 125 –
-40 – 125
°C
°C
Thermal Protection Hysteresis
– 15 – °C
NOTES:
9. Does not include margin limits.
10. Percentage of Full Scale (FS) with temperature compensation applied.
11. VOUT measured at the termination of the VSEN+ and VSEN- sense points.
12. The device requires a delay period following an enable signal and prior to ramping its output. Precise timing mode limits this delay period to
approx 2ms, where in normal mode it may vary up to 4ms.
13. Precise ramp timing mode is only valid when using EN pin to enable the device rather than PMBus enable.
14. The devices may require up to a 4ms delay following the assertion of the enable signal (normal mode) or following the de-assertion of the enable
signal.
15. Factory default Power-Good delay is set to the same value as the soft-start ramp time.
16. Percentage of Full Scale (FS) with temperature compensation applied.
17. tSW = 1/fSW, where fSW is the switching frequency.
18. Normal capacitance of logic pins is 5pF.
19. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
5 FN6876.3
August 29, 2012
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