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PDF 36VF1601C-70-4C-EK Data sheet ( Hoja de datos )
| Número de pieza | 36VF1601C-70-4C-EK | |
| Descripción | SST36VF1601C | |
| Fabricantes | Silicon Storage Technology | |
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16 Mbit (x8/x16) Dual-Bank Flash Memory
SST36VF1601C / SST36VF1602C
FEATURES:
SST36VF1601C / 1602C16Mb (x8/x16) Dual-Bank Flash Memory
Data Sheet
• Organized as 1M x16 or 2M x8
• Dual Bank Architecture
– 16 Mbit Bottom Sector Protection
- SST36VF1601C: 12 Mbit + 4 Mbit
– 16 Mbit Top Sector Protection
- SST36VF1602C: 4 Mbit + 12 Mbit
• Single 2.7-3.6V for Read and Write Operations
• Superior Reliability
– Endurance: 100,000 cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption:
– Active Current: 6 mA typical
– Standby Current: 4 µA typical
– Auto Low Power Mode: 4 µA typical
• Hardware Sector Protection/WP# Input Pin
– Protects the 4 outermost sectors (8 KWord)
in the larger bank by driving WP# low and
unprotects by driving WP# high
• Hardware Reset Pin (RST#)
– Resets the internal state machine to reading
array data
• Byte# Pin
– Selects 8-bit or 16-bit mode
• Sector-Erase Capability
– Uniform 2 KWord sectors
• Chip-Erase Capability
• Block-Erase Capability
– Uniform 32 KWord blocks
www.DataSheet4U.com
• Erase-Suspend / Erase-Resume Capabilities
• Security ID Feature
– SST: 128 bits
– User: 128 bits
• Fast Read Access Time
– 70 ns
• Latched Address and Data
• Fast Erase and Program (typical):
– Sector-Erase Time: 18 ms
– Block-Erase Time: 18 ms
– Chip-Erase Time: 35 ms
– Program Time: 7 µs
• Automatic Write Timing
– Internal VPP Generation
• End-of-Write Detection
– Toggle Bit
– Data# Polling
– Ready/Busy# pin
• CMOS I/O Compatibility
• Conforms to Common Flash Memory Interface (CFI)
• JEDEC Standards
– Flash EEPROM Pinouts and command sets
• Packages Available
– 48-ball TFBGA (6mm x 8mm)
– 48-lead TSOP (12mm x 20mm)
– Non-Pb (lead-free) packages available
• All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
The SST36VF1601C and SST36VF1602C are 1M x16 or
2M x8 CMOS Read/Write Flash Memory manufactured
with SST’s proprietary, high performance CMOS Super-
Flash technology. The split-gate cell design and thick oxide
tunneling injector attain better reliability and manufacturabil-
ity compared with alternate approaches. The devices write
(Program or Erase) with a 2.7-3.6V power supply and con-
form to JEDEC standard pinouts for x8/x16 memories.
Featuring high performance Program, these devices pro-
vide a typical Program time of 7 µsec and use the Toggle
Bit, Data# Polling, or RY/BY# to detect the completion of
the Program or Erase operation. To protect against inad-
vertent write, the devices have on-chip hardware and Soft-
ware Data Protection schemes. Designed, manufactured,
and tested for a wide spectrum of applications, these
devices are offered with a guaranteed endurance of 10,000
cycles. Data retention is rated at greater than 100 years.
These devices are suited for applications that require con-
venient and economical updating of program, configura-
tion, or data memory. For all system applications, the
devices significantly improve performance and reliability,
while lowering power consumption. Since for any given
voltage range, the SuperFlash technology uses less cur-
rent to program and has a shorter erase time, the total
energy consumed during any Erase or Program operation
is less than alternative flash technologies. These devices
also improve flexibility while lowering the cost for program,
data, and configuration storage applications.
©2006 Silicon Storage Technology, Inc.
S71249-06-000
1/06
1
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
1 page  
16 Mbit Dual-Bank Flash Memory
SST36VF1601C / SST36VF1602C
Common Flash Memory Interface (CFI)
These devices also contain the CFI information to
describe the characteristics of the devices. In order to
enter the CFI Query mode, the system must write the
three-byte sequence, same as the Software ID Entry com-
mand with 98H (CFI Query command) to address 555H in
the last byte sequence. See Figure 16 for CFI Entry and
Read timing diagram. Once the device enters the CFI
Query mode, the system can read CFI data at the
addresses given in Tables 6 through 8. The system must
write the CFI Exit command to return to Read mode from
the CFI Query mode.
Security ID
The SST36VF160xC devices offer a 256-bit Security ID
space. The Secure ID space is divided into two 128-bit seg-
ments—one factory programmed segment and one user
programmed segment. The first segment is programmed
and locked at SST with a unique, 128-bit number. The user
segment is left un-programmed for the customer to pro-
gram as desired. To program the user segment of the
Security ID, the user must use the Security ID Program
command. End-of-Write status is checked by reading the
toggle bits. Data# Polling is not used for Security ID End-of-
Write detection. Once programming is complete, the Sec
ID should be locked using the User Sec ID Program Lock-
Out. This disables any future corruption of this space. Note
that regardless of whether or not the Sec ID is locked, nei-
ther Sec ID segment can be erased. The Secure ID space
can be queried by executing a three-byte command
www.DsateaqSuhenetc4eU.wcoitmh Query Sec ID command (88H) at address
555H in the last byte sequence. See Figure 18 for timing
diagram. To exit this mode, the Exit Sec ID command
should be executed. Refer to Table 5 for more details.
Data Sheet
Product Identification
The Product Identification mode identifies the devices and
manufacturer. For details, see Table 2 for software opera-
tion, Figure 15 for the Software ID Entry and Read timing
diagram and Figure 25 for the Software ID Entry command
sequence flowchart. The addresses A19 and A18 indicate a
bank address. When the addressed bank is switched to
Product Identification mode, it is possible to read another
address from the same bank without issuing a new Soft-
ware ID Entry command.
TABLE 2: PRODUCT IDENTIFICATION
Manufacturer’s ID
Device ID
SST36VF1601C
SST36VF1602C
Address
BK0000H
BK0001H
BK0001H
Note: BK = Bank Address (A19-A18)
Data
00BFH
734BH
734AH
T2.0 1249
Product Identification Mode
Exit/CFI Mode Exit
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exit is accom-
plished by issuing the Software ID Exit command
sequence, which returns the device to the Read mode. This
command may also be used to reset the device to the Read
mode after any inadvertent transient condition that appar-
ently causes the device to behave abnormally, e.g., not read
correctly. Please note that the Software ID Exit/CFI Exit
command is ignored during an internal Program or Erase
operation. See Table 5 for the software command code, Fig-
ure 17 for timing waveform and Figure 26 for a flowchart.
FUNCTIONAL BLOCK DIAGRAM
Memory
Address
Address
Buffers
BYTE#
RST#
CE#
WP#
WE#
OE#
RY/BY#
©2006 Silicon Storage Technology, Inc.
Control
Logic
(8 KWord Sector Protection)
SuperFlash Memory
12 Mbit Bank
SuperFlash Memory
4 Mbit Bank
I/O Buffers
1249 B1.0
DQ15/A-1 - DQ0
S71249-06-000
1/06
5
5 Page 
16 Mbit Dual-Bank Flash Memory
SST36VF1601C / SST36VF1602C
Data Sheet
TABLE 3: PIN DESCRIPTION
Symbol Name
Functions
A19-A0
Address Inputs
To provide memory addresses. During Sector-Erase and Hardware Sector Protection,
A19-A11 address lines will select the sector. During Block-Erase A19-A15 address
lines will select the block.
DQ14-DQ0 Data Input/Output
To output data during Read cycles and receive input data during Write cycles
Data is internally latched during a Write cycle. The outputs are in tri-state when
OE# or CE# is high.
DQ15/A-1 Data Input/Output
and LBS Address
DQ15 is used as data I/O pin when in x16 mode (BYTE# = “1”)
A-1 is used as the LSB address pin when in x8 mode (BYTE# = “0”)
CE# Chip Enable
To activate the device when CE# is low.
OE#
Output Enable
To gate the data output buffers
WE#
Write Enable
To control the Write operations
RST#
Hardware Reset
To reset and return the device to Read mode
RY/BY# Ready/Busy#
To output the status of a Program or Erase operation
RY/BY# is a open drain output, so a 10KΩ - 100KΩ pull-up resistor is required
to allow RY/BY# to transition high indicating the device is ready to read.
WP#
Write Protect
To protect and unprotect top or bottom 8 KWord (4 outermost sectors) from Erase or
Program operation.
BYTE# Word/Byte Configuration To select 8-bit or 16-bit mode.
VDD Power Supply
VSS Ground
To provide 2.7-3.6V power supply voltage
NC No Connection
Unconnected pins
T3.2 1249
TABLE 4: OPERATION MODES SELECTION
Mode1
www.DaRtaeSahdeet4U.com
Program
Erase
CE# OE# WE#
VIL VIL VIH
VIL VIH VIL
VIL VIH VIL
DQ7-DQ0
DOUT
DIN
X2
Standby
VIH X
X
High Z
Write Inhibit
X VIL X
High Z / DOUT
X X VIH High Z / DOUT
Product Identification
Software Mode
VIL VIL VIH Manufacturer’s ID
(BFH)
Device ID3
1. RST# = VIH for all described operation modes
2. X can be VIL or VIH, but no other value.
3. Device ID = SST36VF1601C = 734BH,
SST36VF1602C = 734AH
DQ15-DQ8
BYTE# = VIH
BYTE# = VIL
DOUT
DQ14-DQ8 = High Z
DIN DQ15 = A-1
X High Z
High Z
High Z / DOUT
High Z / DOUT
Manufacturer’s ID
(00H)
Device ID3
High Z
High Z
High Z
High Z
High Z
Address
AIN
AIN
Sector or Block
address,
555H for Chip-Erase
X
X
X
See Table 5
T4.2 1249
©2006 Silicon Storage Technology, Inc.
11
S71249-06-000
1/06
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