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PDF ADC10D1500 Data sheet ( Hoja de datos )
| Número de pieza | ADC10D1500 | |
| Descripción | (ADC10D1000 / ADC10D1500) Dual 1.0/1.5 GSPS Or Single 2.0/3.0 GSPS ADC | |
| Fabricantes | National Semiconductor Corporation | |
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ADC10D1000/ADC10D1500
November 19, 2009
Low Power, 10-Bit, Dual 1.0/1.5 GSPS or Single 2.0/3.0
GSPS ADC
1.0 General Description
The ADC10D1000/1500 is the latest advance in National's
Ultra-High-Speed ADC family. This low-power, high-perfor-
mance CMOS analog-to-digital converter digitizes signals at
10-bit resolution for dual channels at sampling rates of up to
1.0/1.5 GSPS (Non-DES Mode) or for a single channel up to
2.0/3.0 GSPS (DES Mode). The ADC10D1000/1500
achieves excellent accuracy and dynamic performance while
dissipating less than 2.8/3.6 Watts. The product is packaged
in a leaded or lead-free 292-ball thermally enhanced BGA
package over the rated industrial temperature range of
-40°C to +85°C.
The ADC10D1000/1500 builds upon the features, architec-
ture and functionality of the 8-bit GHz family of ADCs. An
expanded feature set includes AutoSync for multi-chip syn-
chronization, 15-bit programmable gain and 12-bit plus sign
programmable offset adjustment for each channel. The im-
proved internal track-and-hold amplifier and the extended
self-calibration scheme enable a very flat response of all dy-
namic parameters beyond Nyquist, producing 9.1/9.0 Effec-
tive Number of Bits (ENOB) with a 100 MHz input signal and
a 1.0/1.5 GHz sample rate while providing a 10-18 Code Error
Rate (CER) Dissipating a typical 2.77/3.59 Watts in Non-De-
multiplex Mode at 1.0/1.5 GSPS from a single 1.9V supply,
this device is guaranteed to have no missing codes over the
full operating temperature range.
Each channel has its own independent DDR Data Clock,
DCLKI and DCLKQ, which are in phase when both channels
are powered up, so that only one Data Clock could be used
to capture all data, which is sent out at the same rate as the
input sample clock. If the 1:2 Demux Mode is selected, a sec-
ond 10-bit LVDS bus becomes active for each channel, such
www.DathtaaSt htheeeto4uUtp.cuotmdata rate is sent out two times slower to relax
data-capture timing requirements. The part can also be used
as a single 2.0/3.0 GSPS ADC to sample one of the I or Q
inputs. The output formatting can be programmed to be offset
binary or two's complement and the Low Voltage Differential
Signaling (LVDS) digital outputs are compatible with IEEE
1596.3-1996, with the exception of an adjustable common
mode voltage between 0.8V and 1.2V to allow for power re-
duction for well-controlled back planes.
2.0 Features
■ Excellent accuracy and dynamic performance
■ Low power consumption, further reduced at lower Fs
■ Internally terminated, buffered, differential analog inputs
■ R/W SPI Interface for Extended Control Mode
■ Dual-Edge Sampling Mode, in which the I- and Q-channels
sample one input at twice the sampling clock rate
■ Test patterns at output for system debug
■ Programmable 15-bit gain and 12-bit plus sign offset
■ Programmable tAD adjust feature
■ 1:1 non-demuxed or 1:2 demuxed LVDS outputs
■ AutoSync feature for multi-chip systems
■ Single 1.9V ± 0.1V power supply
■ 292-ball BGA package (27mm x 27mm x 2.4mm with
1.27mm ball-pitch); no heat sink required
■ LC sampling clock filter for jitter reduction
3.0 Key Specifications
(Non-Demux Non-DES Mode, Fs=1.0/1.5 GSPS, Fin = 100
MHz)
■ Resolution
10 Bits
■ Conversion Rate
— Dual channels at 1.0/1.5 GSPS (typ)
— Single channel at 2.0/3.0 GSPS (typ)
■ Code Error Rate
10-18/10-18 (typ)
■ ENOB
9.1/9.0 bits (typ)
■ SNR
57/56.8 dB (typ)
■ SFDR
70/68 dBc (typ)
■ Full Power Bandwidth
2.8/3.1 GHz (typ)
■ DNL
±0.25/±0.25 LSB (typ)
■ Power Consumption
— Single Channel Enabled
— Dual Channels Enabled
— Power Down Mode
1.61/1.92W (typ)
2.77/3.59W (typ)
6/6 mW (typ)
4.0 Applications
■ Wideband Communications
■ Data Acquisition Systems
■ Digital Oscilloscopes
5.0 Ordering Information
Industrial Temperature Range (-40°C < TA < +85°C)
ADC10D1000/1500CIUT/NOPB
ADC10D1000/1500CIUT
ADC10D1000/1500RB
NS Package
Lead-free 292-Ball BGA Thermally Enhanced Package
Leaded 292-Ball BGA Thermally Enhanced Package
Reference Board
If Military/Aerospace specified devices are required, please contract the National Semiconductor Sales Office/Dis-
tributors for availability and specifications. IBIS models are available at: http://www.national.com/analog/adc/
ibis_models.
© 2009 National Semiconductor Corporation 300663
www.national.com
1 page  
TABLE 4. High-Speed Digital Outputs .......................................................................................................... 14
TABLE 5. Package Thermal Resistance ........................................................................................................ 16
TABLE 6. Static Converter Characteristics ..................................................................................................... 16
TABLE 7. Dynamic Converter Characteristics ................................................................................................ 17
TABLE 8. Analog Input/Output and Reference Characteristics ............................................................................. 20
TABLE 9. I-Channel to Q-Channel Characteristics ............................................................................................ 21
TABLE 10. Sampling Clock Characteristics ................................................................................................... 21
TABLE 11. Digital Control and Output Pin Characteristics ................................................................................... 22
TABLE 12. Power Supply Characteristics ...................................................................................................... 23
TABLE 13. AC Electrical Characteristics ........................................................................................................ 24
TABLE 14. Non-ECM Pin Summary ............................................................................................................. 43
TABLE 15. Serial Interface Pins .................................................................................................................. 45
TABLE 16. Command and Data Field Definitions ............................................................................................. 45
TABLE 17. Features and Modes ................................................................................................................ 47
TABLE 18. LC Filter Code vs. fc .................................................................................................................. 49
TABLE 19. LC Filter Bandwidth vs. Level ....................................................................................................... 49
TABLE 20. Test Pattern by Output Port in Demux Mode .................................................................................... 50
TABLE 21. Test Pattern by Output Port in Non-Demux Mode .............................................................................. 50
TABLE 22. Calibration Pins ....................................................................................................................... 50
TABLE 23. Output Latency in Demux Mode ................................................................................................... 52
TABLE 24. Output Latency in Non-Demux Mode ............................................................................................. 52
TABLE 25. Unused AutoSync and DCLK Reset Pin Recommendation ................................................................... 55
TABLE 26. Temperature Sensor Recommendation .......................................................................................... 59
TABLE 27. Amplifier Recommendation ......................................................................................................... 60
TABLE 28. Register Addresses .................................................................................................................. 61
www.DataSheet4U.com
5 www.national.com
5 Page 
Ball No.
Name
U3 PDI
V3 PDQ
A4 TPM
A5 NDM
www.DataSheet4U.com
Y3
FSR
W4 DDRPh
Equivalent Circuit
Description
Power Down I- and Q-channel. Setting either
input to logic-high powers down the respective I-
or Q-channel. Setting either input to logic-low
brings the respective I- or Q-channel to a
operational state after a finite time delay. This pin
is active in both ECM and Non-ECM. In ECM,
each Pin is logically OR'd with its respective Bit.
Therefore, either this pin or the PDI and PDQ Bit
in the Control Register can be used to power-
down the I- and Q-channel (Addr: 0h, Bit 11 and
Bit 10), respectively.
Test Pattern Mode select. With this input at logic-
high, the device continuously outputs a fixed,
repetitive test pattern at the digital outputs. In the
ECM, this input is ignored and the Test Pattern
Mode can only be activated through the Control
Register by the TPM Bit (Addr: 0h, Bit 12).
Non-Demuxed Mode select. Setting this input to
logic-high causes the digital output bus to be in
the 1:1 Non-Demuxed Mode. Setting this input to
logic-low causes the digital output bus to be in the
1:2 Demuxed Mode. This feature is pin-controlled
only and remains active during ECM and Non-
ECM.
Full-Scale input Range select. In Non-ECM,
when this input is set to logic-low or logic-high,
the full-scale differential input range for both I-
and Q-channel inputs is set to the lower or higher
FSR value, respectively. In the ECM, this input is
ignored and the full-scale range of the I- and Q-
channel inputs is independently determined by
the setting of Addr: 3h and Addr: Bh, respective-
ly. Note that the high (lower) FSR value in Non-
ECM corresponds to the mid (min) available
selection in ECM; the FSR range in ECM is
greater.
DDR Phase select. This input, when logic-low,
selects the 0° Data-to-DCLK phase relationship.
When logic-high, it selects the 90° Data-to-DCLK
phase relationship, i.e. the DCLK transition
indicates the middle of the valid data outputs.
This pin only has an effect when the chip is in 1:2
Demuxed Mode, i.e. the NDM pin is set to logic-
low. In ECM, this input is ignored and the DDR
phase is selected through the Control Register by
the DPS Bit (Addr: 0h, Bit 14); the default is 0°
Mode.
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