|
|
PDF T44C080 Data sheet ( Hoja de datos )
| Número de pieza | T44C080 | |
| Descripción | Low-Current Microcontroller | |
| Fabricantes | Atmel Wireless and Microcontrollers | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de T44C080 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
T44C080
Low-Current Microcontroller for Wireless Communication
The T44C080 is a member of Atmel Wireless & Microcontrollers’ family of 4-bit single-chip microcontrollers. It con-
tains ROM, RAM, parallel I/O ports, one 8-bit programmable multifunction timer/counter with modulator function,
voltage supervisor, interval timer with watchdog function and a sophisticated on-chip clock generation with external
clock input, integrated RC-, 32-kHz crystal- and 4-MHz crystal-oscillators.
Features / Benefits
D Very low power consumption in active, power-down
and sleep mode
D 2-Kbyte ROM, 256 x 4-bit RAM
D 12 bidirectional I/Os
D Up to 6 external / internal interrupt sources
D Multifunction timer/counter
D Programmable system-clock with prescaler and five
different clock sources
D Wide supply voltage range (1.8 to 6.5 V)
D Very low sleep current (< 1 µA)
D Synchronous serial interface (2-wire, I2C, 3-wire)
D Watchdog, POR and brown-out function
D Voltage monitoring incl. Lo_BAT detect
D Flash controller T48C893 available (SSO20)
VSS VDD
NRST/
OSC1 OSC2
www.DataSheet4U.com BP20/NTE
BP21
BP22
BP23
Brown-out protect.
RESET
Voltage monitor
External input
VMI
RC Crystal External
oscillators oscillators clock input
Clock management
ROM
RAM
2 K x 8 bit 256 x 4 bit
MARC4
4-bit CPU core
I/O bus
UTCM
Timer 1
interval- and
watchdog timer
Timer 2
8/12-bit timer
with modulator
SSI
Serial interface
T2I
T2O
SD
SC
Data direction +
alternate function
Port 4
Data direction +
interrupt control
Port 5
BP40 BP42
INT3 T2O BP43
SC BP41 INT3
VMI SD
T2I
BP50 BP52
INT6 INT1
BP51 BP53
INT6 INT1
Figure 1. Block diagram of the T44C080
Rev. A2, 15-Jan-01
1 (56)
1 page  
T44C080
1 Introduction
The T44C080 is a member of Atmel Wireless &
Microcontrollers’s family of 4-bit single-chip micro-
controllers. They contain ROM, RAM, parallel I/O ports,
one 8-bit programmable multifunction timer/counter,
voltage supervisor, interval timer with watchdog function
and a sophisticated on-chip clock generation with inte-
grated RC-, 32-kHz crystal- and 4-MHz
crystal-oscillators.
2 MARC4 Architecture
2.1 General Description
The MARC4 microcontroller consists of an advanced
stack-based, 4-bit CPU core and on-chip peripherals. The
CPU is based on the HARVARD architecture with
physically separate program memory (ROM) and data
memory (RAM). Three independent buses, the
instruction bus, the memory bus and the I/O bus, are used
for parallel communication between ROM, RAM and
peripherals. This enhances program execution speed by
allowing both instruction prefetching, and a simultaneous
communication to the on-chip peripheral circuitry. The
extremely powerful integrated interrupt controller with
associated eight prioritized interrupt levels supports fast
and efficient processing of hardware events. The MARC4
is designed for the high-level programming language
qFORTH. The core includes both, an expression and a
return stack. This architecture enables high-level
language programming without any loss of efficiency or
code density.
www.DataSheet4U.comSRcyleossCtcSeeRlkltomeeceskpeÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏt ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏPmÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏreoÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏIcmIgndnosretÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏnoItaecrntrrmurosryoÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏcdutblrtepluuiIeortÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ/scrOntioÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏbMnusÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏAPCÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏRMCeÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏm4oÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏrCCyÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏCbORSXYuRPPÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏsREÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏTOÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏSAÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏL2R5UÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ6AxÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ4M-bÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏit ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
On–chip peripheral modules
Figure 3. MARC4 core
94 8973
Rev. A2, 15-Jan-01
5 (56)
5 Page 
T44C080
Table 2 Interrupt priority table
Interrupt
INT0
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁINT1
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁINT2
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁINT3
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁINT4
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁINT5
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁINT6
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁINT7
Priority
lowest
|
|
|
|
|
↓
highest
ROM Address Interrupt Opcode
040h
C8h (SCALL 040h)
080h
D0h (SCALL 080h)
0C0h
100h
D8h (SCALL 0C0h)
E8h (SCALL 100h)
140h
180h
1C0h
E8h (SCALL 140h)
F0h (SCALL 180h)
F8h (SCALL 1C0h)
1E0h
FCh (SCALL 1E0h)
Function
Software interrupt (SWI0)
External hardware interrupt, any edge at BP52
or BP53
Timer 1 interrupt
SSI interrupt or external hardware interrupt at
BP40 or BP43
Timer 2 interrupt
Software interrupt (SW15)
External hardware interrupt, at any edge at
BP50 or BP51
Voltage monitor (VM) interrupt
Table 3 Hardware interrupts
Interrupt
Interrupt Mask
Interrupt Source
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁINT1
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁINT2
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁINT3
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁINT4
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁINT6
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁINT7
Register
P5CR
T1M
SISC
T2CM
P5CR
VCM
Bit
P52M1, P52M2
P53M1, P53M2
T1IM
SIM
T2IM
P50M1, P50M2
P51M1, P51M2
VIM
Any edge at BP52
any edge at BP53
Timer 1
SSI buffer full / empty or BP40/BP43 interrupt
Timer 2 compare match / overflow
Any edge at BP50,
any edge at BP51
External / internal voltage monitoring
Software Interrupts
The programmer can generate interrupts by using the
software interrupt instruction (SWI) which is supported
in qFORTH by predefined macros named SWI0...SWI7.
The software triggered interrupt operates exactly like any
www.DataShheaerdt4wUa.croemtriggered interrupt. The SWI instruction takes
the top two elements from the expression stack and writes
the corresponding bits via the I/O bus to the interrupt
pending register. Therefore, by using the SWI instruction,
interrupts can be re-prioritized or lower priority processes
scheduled for later execution.
Hardware Interrupts
In the T44C080, there are eleven hardware interrupt
sources with seven different levels. Each source can be
masked individually by mask bits in the corresponding
control registers. An overview of the possible hardware
configurations is shown in table 4.
2.3 Master Reset
The master reset forces the CPU into a well-defined
condition. It is unmaskable and is activated independent
of the current program state. It can be triggered by either
initial supply power-up, a short collapse of the power sup-
ply, brown-out detection circuitry, watchdog time-out, or
an external input clock supervisor stage (see figure 9). A
master reset activation will reset the interrupt enable flag,
the interrupt pending register and the interrupt active
register. During the power-on reset phase the I/O bus con-
trol signals are set to ’reset mode’ thereby initializing all
on-chip peripherals. All bidirectional ports are set to input
mode. Attention: During any reset phase, the BP20/NTE
input is driven towards VDD by a strong pull-up transistor.
Releasing the reset results in a short call instruction
(opcode C1h) to the ROM address 008h. This activates
the initialization routine $RESET which in turn has to
initialize all necessary RAM variables, stack pointers and
peripheral configuration registers (see table 7).
Rev. A2, 15-Jan-01
11 (56)
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet T44C080.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| T44C080 | Low-Current Microcontroller | Atmel Wireless and Microcontrollers |
| T44C080-V | Low-Current Microcontroller | Atmel Wireless and Microcontrollers |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |