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PDF 25L1005MC Data sheet ( Hoja de datos )
| Número de pieza | 25L1005MC | |
| Descripción | MX25L1005MC | |
| Fabricantes | Macronix International | |
| Logotipo |  |
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 1. CMOS 1M bit Flash Memory  Hay una vista previa y un enlace de descarga de 25L1005MC (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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MX25L1005
MX25L1005
DATASHEET
The MX25L1005 product family is not recommended for new designs. The MX25L1005C
family is the recommended replacement. Please refer to MX25L1005C datasheet for
full specifications and ordering information, or contact your local sales representative for
additional support.
P/N: PM1238
REV. 2.0, APR. 15, 2009
1
1 page  
BLOCK DIAGRAM
Address
Generator
MX25L1005
Memory Array
SI
CS#
SCLK
Page Buffer
Data
Register
SRAM
Buffer
Mode
Logic
State
Machine
Y-Decoder
HV
Generator
Sense
Amplifier
Clock Generator
Output
Buffer
SO
P/N: PM1238
REV. 2.0, APR. 15, 2009
5
5 Page 
MX25L1005
COMMAND DESCRIPTION
(1) Write Enable (WREN)
The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, SE,
BE, CE, and WRSR, which are intended to change the device content, should be set every time after the WREN in-
struction setting the WEL bit.
The sequence of issuing WREN instruction is: CS# goes low→ sending WREN instruction code→ CS# goes high. (see
Figure 11)
(2) Write Disable (WRDI)
The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit.
The sequence of issuing WRDI instruction is: CS# goes low→ sending WRDI instruction code→ CS# goes high. (see
Figure 12)
The WEL bit is reset by following situations:
- Power-up
- Write Disable (WRDI) instruction completion
- Write Status Register (WRSR) instruction completion
- Page Program (PP) instruction completion
- Sector Erase (SE) instruction completion
- Block Erase (BE) instruction completion
- Chip Erase (CE) instruction completion
(3) Read Identification (RDID)
The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The MXIC
Manufacturer ID is C2(hex), the memory type ID is 20(hex) as the first-byte device ID, and the individual device ID
of second-byte ID is as followings: 11(hex) for MX25L1005.
The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code → 24-bits ID data out
on SO→ to end RDID operation can use CS# to high at any time during data out. (see Figure. 13)
While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cy-
cle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage.
P/N: PM1238
REV. 2.0, APR. 15, 2009
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 25L1005MC.PDF ] | |
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