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PDF FDMF6700 Data sheet ( Hoja de datos )
| Número de pieza | FDMF6700 | |
| Descripción | Driver plus FET Multi-chip Module | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de FDMF6700 (archivo pdf) en la parte inferior de esta página. Total 13 Páginas | ||
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May 2007
FDMF6700
Driver plus FET Multi-chip Module
tm
Benefits
Fully optimized system efficiency. Higher efficiency levels
are achievable compared with conventional discrete
components.
Space savings of up to 50% PCB versus discrete solutions.
Higher frequency of operation.
Simpler system design and board layout. Reduced time in
component selection and optimization.
Features
12V typical Input Voltage
Output current up to 25A
500KHz switching frequency capable
Internal adaptive gate drive
Integrated bootstrap diode
Peak Efficiency >85%
Under-voltage Lockout
Output disable for lost phase shutdown
Low profile SMD package
RoHS Compliant
General Description
The FDMF6700 is a fully optimized integrated 12V Driver plus
MOSFET power stage solution for high current synchronous
buck DC-DC applications. The device integrates a driver IC and
two Power MOSFETs into a space saving, 6mm x 6mm, 40-pin
Power66™ package. Fairchild Semiconductor’s integrated
approach optimizes the complete switching power stage with
regards to driver to FET dynamic performance, system
inductance and overall solution ON resistance. Package
parasitics and problematical layouts associated with
conventional discrete solutions are greatly reduced. This
integrated approach results in significant board space saving,
therefore maximizing footprint power density. This solution is
based on the Intel™ DrMOS specification.
Applications
Desktop and server VR11.x V-core and non V-core buck
converters.
CPU/GPU power train in game consoles and high end
desktop systems.
High-current DC-DC Point of Load (POL) converters
Networking and telecom microprocessor voltage regulators
Small form factor voltage regulator modules
Powertrain Application Circuit
www.DataSheet4U.com
12V
CVCC
DISB
PWM
Input
VCIN
DISB
VIN
BOOT
PWM
VSWH
CGND PGND
CBOOT
OUTPUT
COUT
Figure 1. Powertrain Application Circuit
Ordering Information
Part
FDMF6700
Current Rating
Max
[A]
25
Input Voltage
Typical
[V]
12
Frequency
Max
[KHz]
500
©2007 Fairchild Semiconductor Corporation
FDMF6700 Rev. B
1
Device
Marking
FDMF6700
www.fairchildsemi.com
1 page  
Typical Characteristics
30
25
20
15
10
VIN = 12V
5
VOUT = 1.3V
fSW = 500KHz
L = 0.68uH
0
0 25 50 75 100 125 150
PCB Temperature, oC
Figure 4. Safe Operating Area vs. PCB Temperature
1.25
1.20
1.15
VIN = 12V
VOUT = 1.3V
IOUT = 25A
L = 0.68uH
1.10
1.05
1.00
0.95
0.90
200 250 300 350 400 450
Switching Frequency, KHz
Figure 6. Power Loss vs. Switching Frequency
www.DataSheet4U.com
500
1.10
1.08
1.05
1.03
1.00
0.98
0.95
VIN = 12V
VOUT = 1.3V
IOUT = 25A
L = 0.68uH
fSW = 300KHz
78
9 10 11
Driver Supply Voltage, V
12
Figure 8. Power Loss vs. Supply Voltage
13
8
VIN = 12V
VOUT = 1.3V
L = 0.68uH
6
4
2
fSW = 500KHz
fSW = 300KHz
0
0
5 10 15 20
ILOAD, A
Figure 5. Module Power Loss vs. Output Current
(VO measured at VSWH pin)
25
1.2
1.1
1.0
VOUT = 1.3V
IOUT = 25A
L = 0.68uH
fSW = 300KHz
0.9
68
10 12
Input Voltage, V
14
Figure 7. Power Loss vs. Input Voltage
16
1.6
VIN = 12V
IOUT = 25A
L = 0.68uH
1.4 fSW = 300KHz
1.2
1.0
0.8
0.8 1.2 1.6 2.0 2.4 2.8
Output Voltage, V
Figure 9. Power Loss vs. Output Voltage
3.2
FDMF6700 Rev. B
5 www.fairchildsemi.com
5 Page 
Module Power Loss Measurement and
Calculation
Refer to Figure 27 for module power loss testing method. Power
loss calculation are as follows:
(a) PIN
(b) POUT
(c) PLOSS
= (VIN x IIN) + (VCIN x ICIN) (W)
= VO x IOUT (W)
= PIN - POUT (W)
PCB Layout Guideline
Figure 28. shows a proper layout example of FDMF6700 and
critical parts. All of high current flow path, such as VIN, VSWH,
VOUT and GND copper, should be short and wide for better and
stable current flow, heat radiation and system performance.
Following is a guideline which the PCB designer should
consider:
1. Input bypass capacitors should be close to VIN and GND pin
of FDMF6700 to help reduce input current ripple component
induced by switching operation.
2. It is critical that the VSWH copper has minimum area for
lower switching noise emission. VSWH copper trace should
also be wide enough for high current flow. Other signal routing
path, such as PWM IN and BOOT signal, should be considered
with care to avoid noise pickup from VSWH copper area.
3. Output inductor location should be as close as possible to the
FDMF6700 for lower power loss due to copper trace.
4. Place ceramic bypass capacitor and boot capacitor as close
to VCIN and BOOT pin of FDMF6700 in order to supply stable
power. Routing width and length should also be considered.
5. Use multiple Vias on each copper area to interconnect each
top, inner and bottom layer to help smooth current flow and heat
conduction. Vias should be relatively large and of reasonable
inductance.
DISB
PWM input
CBOOT
VCIN
VIN
ICIN
A
CVCIN
IIN
A
CVIN
PWM
VCIN
DISB
FDMF6700
BOOT
VSWH
VIN CGND
PGND
L
V VO
IOUT
A
COUT
IC Ground
Power Ground
Figure 27. Power Loss Measurement Block Diagram
VOUT
www.DataSheet4U.com
FDMF6700 Rev. B
Figure 28. Typical PCB Layout Example (Top View)
11
www.fairchildsemi.com
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet FDMF6700.PDF ] | |
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