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PDF WV3EG264M64EFSU-D4 Data sheet ( Hoja de datos )
| Número de pieza | WV3EG264M64EFSU-D4 | |
| Descripción | 1GB - 2x64Mx64 DDR SDRAM UNBUFFERED | |
| Fabricantes | White Electronic Designs | |
| Logotipo |  |
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White Electronic Designs WV3EG264M64EFSU-D4
PRELIMINARY*
1GB – 2x64Mx64 DDR SDRAM UNBUFFERED
FEATURES
PC2700 @ CL2.5
Double-data-rate architecture
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Auto and self refresh, (8K/64ms refresh)
Serial presence detect
Power supply: VCC/VCCQ: 2.5V ± 0.2V
Dual Rank
Standard 200 pin SO-DIMM package
• Package height options:
D4: 31.75 mm (1.25”)
NOTE: Consult factory for availability of:
• RoHS compliant products
• Vendor source control options
• Industrial temperature option
DESCRIPTION
The WV3EG264M64EFSU is a 2x64Mx64 Double Data
Rate SDRAM memory module based on 512Mb DDR
SDRAM component. The module consists of sixteen
64Mx8 bit with 4 banks DDR SDRAMs in FBGA packages
mounted on a 200 pin FR4 substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
* This product is under development, is not qualified or characterized and is subject to
change without notice.
www.DataSheet4U.com
OPERATING FREQUENCIES
Clock Speed
CL-tRCD-tRP
DDR333 @CL=2.5
166MHz
2.5-3-3
August 2005
Rev. 0
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
1 page  
White Electronic Designs WV3EG264M64EFSU-D4
PRELIMINARY
AC OPERATING TEST CONDITIONS
Parameter/Condition
Symbol
Min
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Differential Voltage, CK and CK# inputs
Input Crossing Point Voltage, CK and CK# inputs
VIH(AC)
VIL(AC)
VID(AC)
VIX(AC)
VREF +0.31
0.7
0.5*VCCQ-0.2
NOTES:
1. VIH overshoot: VIH = VCCQ +1.5V for a pulse width < 3ns and the pulse can not be greater than 1/3 of the cycle rate.
VIL undershoot: VIL = -1.5V for a pulse width < 3ns and the pulse can not be greater than 1/3 of the cycle rate.
Max
VREF -0.31
VCCQ+0.6
0.5*VCCQ+0.2
Unit
V
V
V
V
Note
1
1
www.DataSheet4U.com
August 2005
Rev. 0
5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
5 Page 
White Electronic Designs WV3EG264M64EFSU-D4
PRELIMINARY
Document Title
1GB – 2x64Mx64 DDR SDRAM UNBUFFERED
Revision History
Rev #
Rev 0
History
Initial Release
Release Date Status
8-05
Preliminary
www.DataSheet4U.com
August 2005
Rev. 0
11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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