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PDF WV3EG216M64STSU-D4 Data sheet ( Hoja de datos )
| Número de pieza | WV3EG216M64STSU-D4 | |
| Descripción | 256MB - 2x16Mx64 DDR SDRAM UNBUFFERED | |
| Fabricantes | White Electronic Designs | |
| Logotipo |  |
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White Electronic Designs WV3EG216M64STSU-D4
PRELIMINARY*
256MB – 2x16Mx64 DDR SDRAM UNBUFFERED
FEATURES
DESCRIPTION
Double-data-rate architecture
PC2700@CL=2.5
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2,5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto and self refresh, (8K/64ms refresh)
Serial presence detect with EEPROM
Power Supply: VCC/VCCQ: 2.5V ± 0.20V
Dual Rank
Standard 200 pin SO-DIMM package
• Package height options:
D4: 31.75mm (1.25")
NOTE: Consult factory for availability of:
• RoHS compliant products
• Vendor source control options
• Industrial temperature option
www.DataSheet4U.com
The WV3EG216M64STSU is a 2x16Mx64 Double
Data Rate SDRAM memory module based on 256Mb
DDR SDRAM components. The module consists of
eight 16Mx16 DDR SDRAMs in 66 pin TSOP package
mounted on a 200 Pin FR4 substrate.
Synchronous design allows precise cycle control with
the use of system clock. Data I/O transactions are
possible on both edges and Burst Lenths allow the
same device to be useful for a variety of high bandwidth,
high performance memory system applications.
* This product is under development, is not qualified or characterized and is subject to
change without notice.
OPERATING FREQUENCIES
Clock Speed
CL-tRCD-tRP
DDR333@CL=2.5
166MHz
2.5-3-3
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
December 2005
Rev. 1
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
1 page  
White Electronic Designs WV3EG216M64STSU-D4
PRELIMINARY*
AC OPERATING TEST CONDITIONS
Parameter/Condition
Symbol
Min
Max
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Differential Voltage, CK and CK# inputs
Input Crossing Point Voltage, CK and CK# inputs
VIH(AC)
VIL(AC)
VID(AC)
VIX(AC)
VREF +0.31
0.7
0.5*VCCQ-0.2
VREF -0.31
VCCQ+0.6
0.5*VCCQ+0.2
NOTES:
1. VIH overshoot: VIH = VCCQ +1.5V for a pulse width < 3ns and the pulse can not be greater than 1/3 of the cycle rate.
VIL undershoot: VIL = -1.5V for a pulse width < 3ns and the pulse can not be greater than 1/3 of the cycle rate.
Unit
V
V
V
V
Note
1
1
www.DataSheet4U.com
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
August 2005
Rev. 0
5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
5 Page 
White Electronic Designs WV3EG216M64STSU-D4
PRELIMINARY*
Document Title
256MB – 2x16Mx64, DDR SDRAM UNBUFFERED
Revision History
Rev #
Rev 0
Rev 1
History
Created
1.1 Added Samsung IDD specs
Release Date Status
8-05
Preliminary
12-05
Preliminary
www.DataSheet4U.com
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
December 2005
Rev. 1
11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet WV3EG216M64STSU-D4.PDF ] | |
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