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PDF P89LPC912 Data sheet ( Hoja de datos )
| Número de pieza | P89LPC912 | |
| Descripción | (P89LPC912 - P89LPC914) 8-bit microcontrollers | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core
1 kB 3 V Flash with 128-byte RAM
Rev. 03 — 17 December 2004
Product data
1. General description
The P89LPC912/913/914 are single-chip microcontrollers in low-cost 14-pin
packages, based on a high performance processor architecture that executes
instructions in two to four clocks, six times the rate of standard 80C51 devices. Many
system level functions have been incorporated into the P89LPC912/913/914 in order
to reduce component count, board space, and system cost.
2. Features
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s 1 kB byte-erasable Flash code memory organized into 256-byte sectors and
16-byte pages. Single-byte erasing allows any byte(s) to be used as non-volatile
data storage.
s 128-byte RAM data memory.
s Two 16-bit counter/timers. Each timer may be configured to toggle a port output
upon timer overflow or to become a PWM output.
s 23-bit system timer that can also be used as a Real-Time clock.
s Two analog comparators with selectable inputs and reference source.
s Enhanced UART with fractional baudrate generator, break detect, framing error
detection, automatic address detection and versatile interrupt capabilities
(P89LPC913, P89LPC914).
s SPI communication port.
s Internal RC oscillator (factory calibrated to ±1 %) option allows operation without
external oscillator components. The RC oscillator option is selectable and fine
tunable.
s 2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or
driven to 5.5 V).
s Up to 12 I/O pins when using internal oscillator and reset options.
3. Additional features
• 14-pin TSSOP packages.
• A high performance 80C51 CPU provides instruction cycle times of 111 ns to
222 ns for all instructions except multiply and divide when executing at 18 MHz
(167 ns to 333 ns at 12 MHz). This is six times the performance of the standard
80C51 running at the same clock frequency. A lower clock frequency for the same
performance results in power savings and reduced EMI.
• In-Application Programming (IAP-Lite) and byte erase allows code memory to be
used for non-volatile data storage.
1 page  
Philips Semiconductors
P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core
www.DataSheet4U.com
P89LPC913
HIGH PERFORMANCE
ACCELERATED 2-CLOCK 80C51 CPU
1 kB
CODE FLASH
128-BYTE
DATA RAM
INTERNAL BUS
PORT 3
CONFIGURABLE I/Os
PORT 2
CONFIGURABLE I/Os
PORT 1
CONFIGURABLE I/Os
PORT 0
CONFIGURABLE I/Os
KEYPAD
INTERRUPT
PROGRAMMABLE
OSCILLATOR DIVIDER
CPU
CLOCK
CRYSTAL
OR
RESONATOR
CONFIGURABLE
OSCILLATOR
ON-CHIP
RC
OSCILLATOR
Fig 2. P89LPC913 block diagram.
UART
SPI
REAL-TIME CLOCK/
SYSTEM TIMER
TIMER 0
TIMER 1
WATCHDOG TIMER
AND OSCILLATOR
ANALOG
COMPARATORS
POWER MONITOR
(POWER-ON RESET,
BROWNOUT RESET)
002aaa473
9397 750 14468
Product data
Rev. 03 — 17 December 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
5 of 63
5 Page 
Philips Semiconductors
P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core
Table 4: P89LPC913 pin description…continued
Symbol
Pin
Type Description
P2.2, P2.3,
P2.5
I/O Port 2: Port 2 is a 3-bit I/O port with a user-configurable output type. During reset
Port 2 latches are configured in the input only mode with the internal pull-up disabled.
The operation of Port 2 pins as inputs and outputs depends upon the port
configuration selected. Each port pin is configured independently. Refer to Section
9.11.1 “Port configurations” and Table 13 “DC electrical characteristics” for details.
All pins have Schmitt triggered inputs.
Port 2 also provides various special functions as described below:
13 I/O P2.2 — Port 2 bit 2.
I/O MOSI — SPI master out slave in. When configured as master, this pin is output,
when configured as slave, this pin is input.
14 I/O P2.3 — Port 2 bit 3.
I/O MISO — SPI master in slave out. When configured as master, this pin is input, when
configured as slave, this pin is output.
16 I/O P2.5 — Port 2 bit 5.
I/O SPICLK — SPI clock. When configured as master, this pin is output, when
configured as slave, this pin is input.
P3.0 to P3.1
I/O Port 3: Port 3 is a 2-bit I/O port with a user-configurable output type. During reset
Port 3 latches are configured in the input only mode with the internal pull-up disabled.
The operation of Port 3 pins as inputs and outputs depends upon the port
configuration selected. Each port pin is configured independently. Refer to Section
9.11.1 “Port configurations” and Table 13 “DC electrical characteristics” for details.
All pins have Schmitt triggered inputs.
Port 3 also provides various special functions as described below:
8 I/O P3.0 — Port 3 bit 0.
O XTAL2 — Output from the oscillator amplifier (when a crystal oscillator option is
selected via the FLASH configuration).
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O CLKOUT — CPU clock divided by 2 when enabled via SFR bit (ENCLK - TRIM.6). It
can be used if the CPU clock is the internal RC oscillator, Watchdog oscillator or
external clock input, except when XTAL1/XTAL2 are used to generate clock source
for the Real-Time clock/system timer.
7 I/O P3.1 — Port 3 bit 1.
I XTAL1 — Input to the oscillator circuit and internal clock generator circuits (when
selected via the FLASH configuration). It can be a port pin if internal RC oscillator or
Watchdog oscillator is used as the CPU clock source, and if XTAL1/XTAL2 are not
used to generate the clock for the Real-Time clock/system timer.
VSS 4 I Ground: 0 V reference.
VDD 10 I Power Supply: This is the power supply voltage for normal operation as well as Idle
and Power-down modes.
9397 750 14468
Product data
Rev. 03 — 17 December 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
11 of 63
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| PDF Descargar | [ Datasheet P89LPC912.PDF ] | |
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