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PDF FAN6300 Data sheet ( Hoja de datos )
| Número de pieza | FAN6300 | |
| Descripción | Highly Integrated Quasi-Resonant Current Mode PWM Controller | |
| Fabricantes | Fairchild Semiconductor | |
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June 2008
FAN6300
Highly Integrated Quasi-Resonant Current Mode
PWM Controller
Features
High-Voltage Startup
Quasi-Resonant Operation
Cycle-by-Cycle Current Limiting
Peak-Current-Mode Control
Leading-Edge Blanking
Internal Minimum tOFF
Internal 2ms Soft-Start
Over-Power Compensation
GATE Output Maximum Voltage
Auto-Recovery Short-Circuit Protection (FB Pin)
Auto-Recovery Open-Loop Protection (FB Pin)
VDD Pin & Output Voltage (DET Pin) OVP Latched
Applications
AC/DC NB Adapters
Open-Frame SMPS
www.DataSheet4U.com
Description
The highly integrated FAN6300 PWM controller
provides several features to enhance the performance
of flyback converters. A built-in HV startup circuit can
provide more startup current to reduce the startup time
of the controller. Once the VDD voltage exceeds the
turn-on threshold voltage, the HV startup function is
disabled immediately to improve power consumption.
An internal valley voltage detector ensures the power
system operates at Quasi-Resonant operation in wide-
range line voltage and any load conditions and reduces
switching loss to minimize switching voltage on drain of
power MOSFET.
To minimize standby power consumption and light-load
efficiency, a proprietary green-mode function provides
off-time modulation to decrease switching frequency
and perform extended valley voltage switching to keep
to a minimum switching voltage.
FAN6300 controller also provides many protection
functions. Pulse-by-pulse current limiting ensures the
fixed peak current limit level, even when a short circuit
occurs. Once an open-circuit failure occurs in the
feedback loop, the internal protection circuit disables
PWM output immediately. As long as VDD drops below
the turn-off threshold voltage, controller also disables
PWM output. The gate output is clamped at 18V to
protect the power MOS from high gate-source voltage
conditions. The minimum tOFF time limit prevents the
system frequency from being too high. If the DET pin
reaches OVP, internal OTP is triggered, and the power
system enters latch-mode until AC power is removed.
FAN6300 controller is available in both 8-pin DIP and
SOP packages.
Ordering Information
Part
Number
FAN6300DZ
FAN6300SZ
Operating
Temperature Range
-40 to +105°C
-40 to +105°C
Eco Status
RoHS
RoHS
Package
Packing
Method
8-Lead, Dual Inline Package (DIP)
Tube
8-Lead, Small Outline Package (SOP) Reel & Tape
For Fairchild’s definition of “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
© 2007 Fairchild Semiconductor Corporation
FAN6300 • Rev. 1.0.1
www.fairchildsemi.com
1 page  
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
Max.
Unit
VDD DC Supply Voltage
30 V
VHV HV Pin
500 V
VH GATE Pin
-0.3 25.0
V
VL VFB, VCS, VDET
-0.3 7.0
V
PD Power Dissipation
SOP-8
DIP-8
400 mW
800 mW
TJ Operating Junction Temperature
+150
°C
TSTG
Storage Temperature Range
-55 +150 °C
TL Lead Temperature, Soldering 10 Seconds
+270
°C
ESD
ESD Capability, Human Body Model
ESD Capability, Machine Model
2.0 KV
200 V
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
2. All voltage values, except differential voltages, are given with respect to GND pin.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
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Symbol
Parameter
Min.
Max.
Unit
TA Operating Ambient Temperature
-40 +105 °C
© 2007 Fairchild Semiconductor Corporation
FAN6300 • Rev. 1.0.1
5
www.fairchildsemi.com
5 Page 
Current Sensing and PWM Current Limiting
Peak-current-mode control is utilized to regulate output
voltage and provide pulse-by-pulse current limiting. The
switch current is detected by a sense resistor into the
CS pin. The PWM duty cycle is determined by this
current sense signal and VFB. When the voltage on CS
pin reaches around VLIMIT = (VFB-1.2)/3, the switch cycle
is terminated immediately. VLIMIT is internally clamped to
a variable voltage around 0.8V for output power limit.
Leading Edge Blanking (LEB)
Each time the power MOFFET switches on, a turn-on
spike occurs on the sense resistor. To avoid premature
termination of the switching pulse, lead-edge blanking
time is built in. During the blanking period, the current limit
comparator is disabled; it cannot switch off the gate driver.
Under-Voltage Lockout (UVLO)
The turn-on, PWM-off, and turn-off thresholds are fixed
internally at 16/10/8V. During startup, the startup
capacitor must be charged to 16V through the startup
resistor to enable the IC. The hold-up capacitor
continues to supply VDD until energy can be delivered
from the auxiliary winding of the main transformer. VDD
must not drop below 10V during this startup process.
This UVLO hysteresis window ensures that hold-up
capacitor is adequate to supply VDD during startup.
VDD Over-Voltage Protection
VDD over-voltage protection prevents damage due to
abnormal conditions. Once the VDD voltage is over the
VDD over-voltage protection voltage (VDD-OVP) and lasts
for tVDDOVP, the PWM pulse is disabled until the VDD
voltage drops below the UVLO, then starts again.
Output Over-Voltage Protection
The output over-voltage protection works by the
sampling voltage, as shown in Figure 23, after switch-off
sequence. A 4μs blanking time ignores the leakage
inductance ringing. A voltage comparator and a 2.5V
reference voltage develop an output OVP protection.
The ratio of the divider determines the sampling voltage
of the stop gate, as an optical coupler and secondary
shunt regulator are used. If the DET pin OVP is
triggered, power system enters latch-mode until AC
power is removed.
Gate Output
The BiCMOS output stage is a fast totem-pole gate
driver. Cross conduction has been avoided to minimize
heat dissipation, increase efficiency, and enhance
reliability. The output driver is clamped by an internal
18V Zener diode to protect power MOSFET transistors
against undesired over-voltage gate signals.
Over-Power Compensation
www.DataShTeoet4cUom.copmensate this variation for wide AC input range,
the DET pin produces an offset voltage to compensate
the threshold voltage of the peak current limit to provide
a constant-power limit. The offset is generated in
accordance with the input voltage when PWM signal is
enabled. This results in a lower current limit at high-line
inputs than low-line inputs. At fixed-load condition, the
CS limit is higher when the value of RDET is higher. RDET
also affects the H/L line constant power limit.
Figure 23. Voltage Sampled After 4μs Blanking Time
After Switch-off Sequence
Short-Circuit and Open-Loop Protection
The FB voltage increases every time the output of the
power supply is shorted or overloaded. If the FB voltage
remains higher than a built-in threshold for longer than
tD-OLP, PWM output is turned off. As PWM output is
turned-off, the supply voltage VDD begins decreasing.
When VDD goes below the PWM-off threshold of 10V,
VDD decreases to 8V, then the controller is totally shut
down. VDD is charged up to the turn-on threshold voltage
of 16V through the startup resistor until PWM output is
restarted. This protection feature continues as long as
the overloading condition persists. This prevents the
power supply from overheating due to overloading.
Figure 22. H/L Line Constant Power Limit
Compensated by DET Pin
© 2007 Fairchild Semiconductor Corporation
FAN6300 • Rev. 1.0.1
11
www.fairchildsemi.com
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet FAN6300.PDF ] | |
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