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PDF PE3340 Data sheet ( Hoja de datos )
| Número de pieza | PE3340 | |
| Descripción | Integer-N PLL | |
| Fabricantes | Peregrine Semiconductor | |
| Logotipo |  |
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Product Description
Peregrine’s PE3340 is a high performance integer-N PLL
capable of frequency synthesis up to 3.0 GHz. The
superior phase noise performance of the PE3340 makes
it ideal for applications such as wireless local loop
basestations, LMDS systems and other demanding
terrestrial systems.
The PE3340 features a 10/11 dual modulus prescaler,
counters and a phase comparator as shown in Figure 1.
Counter values are programmable through a three wire
serial interface.
Fabricated in Peregrine’s patented UTSi® (Ultra Thin
Silicon) CMOS technology, the PE3340 offers excellent
RF performance with the economy and integration of
conventional CMOS.
PRODUCT SPECIFICATION
PE3340
3.0 GHz Integer-N PLL for Low
Phase Noise Applications
Features
• 3.0 GHz operation
• ÷10/11 dual modulus prescaler
• Internal phase detector
• Serial programmable
• Low power ⎯ 20 mA at 3 V
• Ultra-low phase noise
• Available in 20-lead TSSOP
Figure 1. Block Diagram
www.DataSheet4U.comFin
Fin
Prescaler
10/11
Sdata
Primary
20-bit
Latch 20
Secon-
dary
20-bit
Latch
20
20
fr
Main
Counter
13
66
R Counter
Phase
Detector
PD_U
PD_D
PEREGRINE SEMICONDUCTOR CORP. ® | http://www.psemi.com
Copyright © Peregrine Semiconductor Corp. 2004
Page 1 of 12
1 page  
PE3340
Advance Information
Table 6. AC Characteristics
VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified
Symbol
Parameter
Conditions
Control Interface and Latches (see Figures 3, 4)
fClk Serial data clock frequency
(Note 1)
tClkH Serial clock HIGH time
tClkL Serial clock LOW time
tDSU Sdata set-up time to Sclk rising edge
tDHLD
Sdata hold time after Sclk rising edge
tPW S_WR pulse width
tCWR Sclk rising edge to S_WR rising edge
tCE Sclk falling edge to E_WR transition
tWRC S_WR falling edge to Sclk rising edge
tEC E_WR transition to Sclk rising edge
Main Divider (Including Prescaler)
Fin Operating frequency
PFin Input level range
External AC coupling
Main Divider (Prescaler Bypassed)
Fin Operating frequency
PFin Input level range
External AC coupling
Reference Divider
fr Operating frequency
(Note 3)
Pfr Reference input power (Note 2)
Single ended input
Phase Detector
fc Comparison frequency
(Note 3)
SSB Phase Noise (Fin = 1.3 GHz, fr = 10 MHz, fc = 1.25 MHz, LBW = 70 kHz, VDD = 3.0 V, Temp = -40° C)
www.DataSheet4U.com
100 Hz Offset
1 kHz Offset
Min Max Units
10 MHz
30 ns
30 ns
10 ns
10 ns
30 ns
30 ns
30 ns
30 ns
30 ns
500
3000
MHz
-5 5 dBm
50 300 MHz
-5 5 dBm
100 MHz
-2 dBm
20 MHz
-75 dBc/Hz
-85 dBc/Hz
Note 1: fclk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify fclk
specification.
Note 2: CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5 Vp-p. For optimum phase
noise performance, the reference input falling edge rate should be faster than 80mV/ns.
Note 3: Parameter is guaranteed through characterization only and is not tested.
PEREGRINE SEMICONDUCTOR CORP. ® | http://www.psemi.com
Copyright © Peregrine Semiconductor Corp. 2004
Page 5 of 12
5 Page 
PE3340
Advance Information
Table 10. Ordering Information
Order
Code
3340-11
3340-12
3340-00
Part Marking
Description
PE3340
PE3340
PE3340EK
PE3340-20TSSOP-74A
PE3340-20TSSOP-200C
PE3340-20TSSOP-EVAL KIT
Package
20-lead TSSOP
20-lead TSSOP
20-lead TSSOP
Shipping
Method
74 units / Tube
2000 units / T&R
1 / Box
www.DataSheet4U.com
PEREGRINE SEMICONDUCTOR CORP. ® | http://www.psemi.com
Copyright © Peregrine Semiconductor Corp. 2004
Page 11 of 12
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet PE3340.PDF ] | |
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