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PDF AD7949 Data sheet ( Hoja de datos )
| Número de pieza | AD7949 | |
| Descripción | 250 kSPS PulSAR ADC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
14-bit resolution with no missing codes
8-channel multiplexer with choice of inputs
Unipolar single-ended
Differential (GND sense)
Pseudobipolar
Throughput: 250 kSPS
INL/DNL: ±0.5/±0.25 LSB typical
SINAD: 85 dB @ 20 kHz
THD: −100 dB @ 20 kHz
Analog input range: 0 V to VREF with VREF up to VDD
Multiple reference types
Internal selectable 2.5 V or 4.096 V
External buffered (up to 4.096 V)
External (up to VDD)
Internal temperature sensor (TEMP)
Channel sequencer, selectable 1-pole filter, busy indicator
No pipeline delay, SAR architecture
Single-supply 2.3 V to 5.5 V operation with
1.8 V to 5.5 V logic interface
Serial interface compatible with SPI, MICROWIRE,
QSPI, and DSP
Power dissipation
2.9 mW @ 2.5 V/200 kSPS
10.8 mW @ 5 V/250 kSPS
Standby current: 50 nA
20-lead 4 mm × 4 mm LFCSP package
APPLICATIONS
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Multichannel system monitoring
Battery-powered equipment
Medical instruments: ECG/EKG
Mobile communications: GPS
Power line monitoring
Data acquisition
Seismic data acquisition systems
Instrumentation
Process control
14-Bit, 8-Channel,
250 kSPS PulSAR ADC
AD7949
FUNCTIONAL BLOCK DIAGRAM
0.5V TO VDD – 0.5V 0.5V TO VDD
0.1µF
10µF
2.3V TO 5.5V
REFIN
REF
VDD
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
COM
BAND GAP
REF
TEMP
SENSOR
AD7949
MUX
14-BIT SAR SPI SERIAL
ADC
INTERFACE
ONE-POLE
LPF
SEQUENCER
GND
1.8V
VIO TO
VDD
CNV
SCK
SDO
DIN
Figure 1.
Table 1. Multichannel 14-/16-Bit PulSAR® ADCs
Type
Channels 250 kSPS 500 kSPS ADC Driver
14-Bit 8
AD7949
ADA4841-x
16-Bit 4
AD7682
ADA4841-x
16-Bit 8
AD7689 AD7699 ADA4841-x
GENERAL DESCRIPTION
The AD7949 is an 8-channel, 14-bit, charge redistribution
successive approximation register (SAR) analog-to-digital
converter (ADC) that operates from a single power supply, VDD.
The AD7949 contains all components for use in a multichannel,
low power data acquisition system, including a true 14-bit SAR
ADC with no missing codes; an 8-channel, low crosstalk
multiplexer that is useful for configuring the inputs as single-
ended (with or without ground sense), differential, or bipolar;
an internal low drift reference (selectable 2.5 V or 4.096 V) and
buffer; a temperature sensor; a selectable one-pole filter; and a
sequencer that is useful when channels are continuously
scanned in order.
The AD7949 uses a simple SPI interface for writing to the
configuration register and receiving conversion results. The SPI
interface uses a separate supply, VIO, which is set to the host
logic level. Power dissipation scales with throughput.
The AD7949 is housed in a tiny 20-lead LFCSP with operation
specified from −40°C to +85°C.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2008–2009 Analog Devices, Inc. All rights reserved.
1 page  
TIMING SPECIFICATIONS
VDD = 4.5 V to 5.5 V, VIO = 1.8 V to VDD, all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter1
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
Time Between Conversions
Data Write/Read During Conversion
CNV Pulse Width
SCK Period
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
VIO Above 2.7 V
VIO Above 2.3 V
VIO Above 1.8 V
CNV Low to SDO D15 MSB Valid
VIO Above 2.7 V
VIO Above 2.3 V
VIO Above 1.8 V
CNV High or Last SCK Falling Edge to SDO High Impedance
CNV Low to SCK Rising Edge
DIN Valid Setup Time from SCK Rising Edge
DIN Valid Hold Time from SCK Rising Edge
Symbol
tCONV
tACQ
tCYC
tDATA
tCNVH
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
Min Typ
1.8
4.0
10
tDSDO + 2
11
11
4
tEN
tDIS
tCLSCK
tSDIN
tHDIN
10
5
5
1 See Figure 2 and Figure 3 for load conditions.
AD7949
Max Unit
2.2 μs
μs
μs
1.0 μs
ns
ns
ns
ns
ns
18 ns
23 ns
28 ns
18 ns
22 ns
25 ns
32 ns
ns
ns
ns
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Rev. B | Page 5 of 32
5 Page 
–60
–70
–80
–90
–100
–110
–120
0
VDD = VREF = 5V, –0.5dB
VDD = VREF = 2.5V, –0.5dB
VDD = VREF = 2.5V, –10dB
VDD = VREF = 5V, –10dB
50 100 150
FREQUENCY (kHz)
Figure 17. THD vs. Frequency
200
90
89 fIN = 20kHz
88
87
86 VDD = VREF = 5V
85
84 VDD = VREF = 2.5V
83
82
81
80
79
78
–10
–8 –6 –4
INPUT LEVEL (dB)
Figure 18. SNR vs. Input Level
–2
0
2
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1
0
–1 UNIPOLAR ZERO
UNIPOLAR GAIN
BIPOLAR ZERO
BIPOLAR GAIN
–2
–55 –35 –15
5 25 45 65
TEMPERATURE (°C)
85 105 125
Figure 19. Offset and Gain Errors vs. Temperature
AD7949
2750
2500
2250
2000
2.5V INTERNAL REF
4.096V INTERNAL REF
INTERNAL BUFFER, TEMP ON
INTERNAL BUFFER, TEMP OFF
EXTERNAL REF, TEMP ON
EXTERNAL REF, TEMP OFF
VIO
fS = 200kSPS
100
90
80
70
1750
60
1500
50
1250
40
1000
30
750
2.5
3.0 3.5 4.0 4.5 5.0
VDD SUPPLY (V)
Figure 20. Operating Currents vs. Supply
3000
2750
fS = 200kSPS
20
5.5
180
160
2500
2250
VDD = 5V, INTERNAL 4.096V REF
140
120
2000
1750
VDD = 5V, EXTERNAL REF
100
80
1500
1250
VDD = 2.5, EXTERNAL REF
VIO
60
40
1000
–55
–35 –15
5 25 45 65
TEMPERATURE (°C)
85 105
Figure 21. Operating Currents vs. Temperature
20
125
25
20 VDD = 2.5V, 85°C
15
VDD = 2.5V, 25°C
10
VDD = 5V, 85°C
5 VDD = 5V, 25°C
VDD = 3.3V, 85°C
VDD = 3.3V, 25°C
0
0 20 40 60 80 100 120
SDO CAPACITIVE LOAD (pF)
Figure 22. tDSDO Delay vs. SDO Capacitance Load and Supply
Rev. B | Page 11 of 32
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD7949.PDF ] | |
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