PDF ADIS16362 Data sheet ( Hoja de datos )

Número de pieza	ADIS16362
Descripción	Six Degrees of Freedom Inertial Sensor
Fabricantes	Analog Devices
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Six Degrees of Freedom Inertial Sensor ADIS16362 FEATURES Triaxis digital gyroscope with digital range scaling ±75°/sec, ±150°/sec, ±300°/sec settings Tight orthogonal alignment: <0.05° Triaxis digital accelerometer: ±1.7 g Autonomous operation and data collection No external configuration commands required Start-up time: 180 ms Sleep mode recovery time: 4 ms Factory-calibrated sensitivity, bias, and axial alignment Calibration temperature range: −20°C to +70°C SPI-compatible serial interface Embedded temperature sensor Programmable operation and control Automatic and manual bias correction controls Bartlett window FIR filter length, number of taps Digital I/O: data ready, alarm indicator, general-purpose Alarms for condition monitoring Sleep mode for power management DAC output voltage Enable external sample clock input: up to 1.2 kHz Single-command self-test Single-supply operation: 4.75 V to 5.25 V 2000 g shock survivability Operating temperature range: −40°C to +105°C APPLICATIONS Medical instrumentation www.DaRtoabSohetiects4U.com Platform control Navigation GENERAL DESCRIPTION The ADIS16362 iSensor® is a complete inertial system that includes a triaxis gyroscope and triaxis accelerometer. Each sensor in the ADIS16362 combines industry-leading iMEMS® technology with signal conditioning that optimizes dynamic performance. The factory calibration characterizes each sensor for sensitivity, bias, alignment, and linear acceleration (gyro bias). As a result, each sensor has its own dynamic compensation formulas that provide accurate sensor measurements over a temperature range of −20°C to +70°C. The ADIS16362 provides a simple, cost-effective method for integrating accurate, multiaxis, inertial sensing into industrial systems, especially when compared with the complexity and investment associated with discrete designs. All necessary Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. FUNCTIONAL BLOCK DIAGRAM AUX_ ADC AUX_ DAC TEMPERATURE SENSOR TRIAXIS MEMS ANGULAR RATE SENSOR SIGNAL CONDITIONING AND CONVERSION CALIBRATION AND DIGITAL PROCESSING OUTPUT REGISTERS AND SPI INTERFACE TRIAXIS MEMS ACCELERATION SENSOR SELF-TEST ADIS16362 ALARMS DIGITAL CONTROL POWER MANAGEMENT RST DIO1 DIO2 DIO3 DIO4/ CLKIN Figure 1. CS SCLK DIN DOUT VCC GND motion testing and calibration are part of the production process at the factory, greatly reducing system integration time. Tight orthogonal alignment simplifies inertial frame alignment in navigation systems. An improved SPI interface and register structure provide faster data collection and configuration control. The ADIS16362 uses a compatible pinout and the same package as the ADIS1635x family. Therefore, systems that currently use the ADIS1635x family can upgrade their performance with minor firmware adjustments in their processor designs. This compact module is approximately 23 mm × 23 mm × 23 mm and provides a flexible connector interface that enables multiple mounting orientation options. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. 1 page ADIS16362 TIMING SPECIFICATIONS TA = 25°C, VCC = 5 V, unless otherwise noted. Table 2. Parameter fSCLK tSTALL tREADRATE tCS tDAV tDSU tDHD tSCLKR, tSCLKF tDR, tDF tSFS t1 tx t2 t3 Description Serial clock Stall period between data Read rate Chip select to clock edge DOUT valid after SCLK edge DIN setup time before SCLK rising edge DIN hold time after SCLK rising edge SCLK rise/fall times DOUT rise/fall times CS high after SCLK edge Input sync positive pulse width Input sync low time Input sync to data ready output Input sync period Normal Mode (SMPL_PRD ≤ 0x09) Min1 Typ Max 0.01 2.0 9 40 48.8 100 24.4 48.8 5 12.5 5 12.5 5 5 100 600 833 1 Guaranteed by design and characterization, but not tested in production. Low Power Mode (SMPL_PRD ≥ 0x0A) Min1 Typ Max 0.01 0.3 75 100 48.8 100 24.4 48.8 5 12.5 5 12.5 5 Burst Read Min1 Typ Max 0.01 1.0 1/fSCLK 48.8 100 24.4 48.8 5 12.5 5 12.5 5 5 100 600 833 Unit MHz μs μs ns ns ns ns ns ns ns μs μs μs μs TIMING DIAGRAMS CS SCLK tCS 1 DOUT www.DataSheet4U.com DIN MSB R/W 23 4 56 tDAV DB14 tDSU DB13 DB12 tDHD DB11 DB10 A6 A5 A4 A3 A2 Figure 2. SPI Timing and Sequence tREADRATE tSTALL CS 15 16 tSFS DB2 DB1 LSB D2 D1 LSB SCLK SYNC CLOCK (DIO4) DATA READY Figure 3. Stall Time and Data Rate t3 t1 tX t2 Figure 4. Input Clock Timing Diagram Rev. 0 \| Page 5 of 20 5 Page ADIS16362 BURST READ DATA COLLECTION Burst read data collection is a process-efficient method for collect- ing data from the ADIS16362. In burst read, all output registers are clocked out on DOUT, 16 bits at a time, in sequential data cycles (each separated by one SCLK period). To start a burst read sequence, set DIN = 0x3E00. The contents of each output register are then shifted out on DOUT, starting with SUPPLY_OUT and ending with AUX_ADC (see Figure 13). The addressing sequence shown in Table 8 determines the order of the outputs in burst read. OUTPUT DATA REGISTERS Each output data register uses the format in Figure 12 and Table 9. Figure 6 shows the positive direction for each inertial sensor. The ND bit is equal to 1 when the register contains unread data. The EA bit is high when any error/alarm flag in the DIAG_STAT register is equal to 1. MSB FOR 14-BIT OUTPUT ND EA MSB FOR 12-BIT OUTPUT Figure 12. Output Register Bit Assignments Table 9. Output Data Register Formats Register Bits Scale Reference SUPPLY_OUT 12 2.418 mV See Table 10 XGYRO_OUT1 14 0.05°/sec See Table 11 YGYRO_OUT1 14 0.05°/sec See Table 11 ZGYRO_OUT1 14 0.05°/sec See Table 11 XACCL_OUT 14 0.333 mg See Table 12 YACCL_OUT 14 0.333 mg See Table 12 ZACCL_OUT 14 0.333 mg See Table 12 XTEMP_OUT2 12 0.136°C See Table 13 YTEMP_OUT2 12 0.136°C See Table 13 ZTEMP_OUT2 12 www.DaAtUaXS_hAeeDtC4U.com 12 0.136°C 805.8 μV See Table 13 See Table 14 1 Assumes that the scaling is set to ±300°/sec. This factor scales with the range. 2 0x0000 = 25°C (±5°C). Table 10. Power Supply, Offset Binary Format Supply Voltage Decimal Hex Binary 5.25 V 2171 LSB 0x87B XXXX 1000 0111 1011 5.002418 V 2069 LSB 0x815 XXXX 1000 0001 0101 5 V 2068 LSB 0x814 XXXX 1000 0001 0100 4.997582 V 2067 LSB 0x813 XXXX 1000 0001 0011 4.75 V 1964 LSB 0x7AC XXXX 0111 1010 1100 Table 11. Rotation Rate, Twos Complement Format Rotation Rate Decimal Hex Binary +300°/sec +6000 LSB 0x1770 XX01 0111 0111 0000 +0.1°/sec +2 LSB 0x0002 XX00 0000 0000 0010 +0.05°/sec +1 LSB 0x0001 XX00 0000 0000 0001 0°/sec 0 LSB 0x0000 XX00 0000 0000 0000 −0.05°/sec −1 LSB 0x3FFF XX11 1111 1111 1111 −0.1°/sec −2 LSB 0x3FFE XX11 1111 1111 1110 −300°/sec −6000 LSB 0x2890 XX10 1000 1001 0000 Table 12. Acceleration, Twos Complement Format Acceleration Decimal Hex Binary +1.7 g +5105 LSB 0x13F1 XX01 0011 1111 0001 +0.667 mg +2 LSB 0x0002 XX00 0000 0000 0010 +0.333 mg +1 LSB 0x0001 XX00 0000 0000 0001 0g 0 LSB 0x0000 XX00 0000 0000 0000 −0.333 mg −1 LSB 0x3FFF XX11 1111 1111 1111 −0.667 mg −2 LSB 0x3FFE XX11 1111 1111 1110 −1.7 g −5105 LSB 0x2C0F XX10 1100 0000 1111 Table 13. Temperature, Twos Complement Format Temperature Decimal Hex Binary +105°C +588 LSB 0x24C XXXX 0010 0100 1100 +85°C +441 LSB 0x1B9 XXXX 0001 1011 1001 +25.272°C +2 LSB 0x002 XXXX 0000 0000 0010 +25.136°C +1 LSB 0x001 XXXX 0000 0000 0001 +25°C 0 LSB 0x000 XXXX 0000 0000 0000 +24.864°C −1 LSB 0xFFF XXXX 1111 1111 1111 +24.728°C −2 LSB 0xFFE XXXX 1111 1111 1110 −40°C −478 LSB 0xE22 XXXX 1110 0010 0010 Table 14. Analog Input, Offset Binary Format Input Voltage Decimal Hex Binary 3.3 V 4095 LSB 0xFFF XXXX 1111 1111 1111 1 V 1241 LSB 0x4D9 XXXX 0100 1101 1001 1.6116 mV 2 LSB 0x002 XXXX 0000 0000 0010 805.8 μV 1 LSB 0x001 XXXX 0000 0000 0001 0V 0 LSB 0x000 XXXX 0000 0000 0000 CS 1 2 34 5 12 SCLK DIN 0x3E00 DON’T CARE DOUT PREVIOUS SUPPLY_OUT XGYRO_OUT YGYRO_OUT ZGYRO_OUT AUX_ADC NOTES 1. THE DOUT LINE HAS BEEN SIMPLIFIED FOR SPACE CONSTRAINTS BUT, IDEALLY, SHOULD INCLUDE ALL REGISTERS FROM SUPPLY_OUT THROUGH AUX_ADC. Figure 13. Burst Read Sequence Rev. 0 \| Page 11 of 20 11 Page

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