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SC16C550B fiches techniques PDF

NXP Semiconductors - UART

Numéro de référence SC16C550B
Description UART
Fabricant NXP Semiconductors 
Logo NXP Semiconductors 





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SC16C550B fiche technique
SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
Rev. 6 — 16 December 2014
Product data sheet
1. General description
The SC16C550B is a Universal Asynchronous Receiver and Transmitter (UART) used for
serial data communications. Its principal function is to convert parallel data into serial data,
and vice versa. The UART can handle serial data rates up to 3 Mbit/s.
The SC16C550B is pin compatible with the ST16C550, TL16C550 and PC16C550, and it
will power-up to be functionally equivalent to the 16C450. The SC16C550B also provides
DMA mode data transfers through FIFO trigger levels and the TXRDY and RXRDY
signals (TXRDY and RXRDY are not supported in the HVQFN32 package). On-board
status registers provide the user with error indications, operational status, and modem
interface control. System interrupts may be tailored to meet user requirements. An internal
loopback capability allows on-board diagnostics.
The SC16C550B operates at 5 V, 3.3 V and 2.5 V, and the Industrial temperature range,
and is available in plastic HVQFN32, DIP40, PLCC44 and LQFP48 packages.
2. Features and benefits
5 V, 3.3 V and 2.5 V operation
Industrial temperature range
After reset, all registers are identical to the typical 16C450 register set
Capable of running with all existing generic 16C450 software
Pin compatibility with the industry-standard ST16C450/550, TL16C450/550,
PC16C450/550
Up to 3 Mbit/s transmit/receive operation at 5 V, 2 Mbit/s at 3.3 V, and 1 Mbit/s at 2.5 V
5 V tolerant on input only pins1
16 byte transmit FIFO
16 byte receive FIFO with error flags
Programmable auto-RTS and auto-CTS
In auto-CTS mode, CTS controls transmitter
In auto-RTS mode, RX FIFO contents and threshold control RTS
Automatic hardware flow control
Software selectable baud rate generator
Four selectable Receive FIFO interrupt trigger levels
Standard modem interface
Standard asynchronous error and framing bits (Start, Stop, and Parity Overrun Break)
Independent receiver clock input
Transmit, Receive, Line Status, and Data Set interrupts independently controlled
1. For data bus pins D7 to D0, see Table 24 “Limiting values”.

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