DataSheetWiki


LF9502 fiches techniques PDF

LOGIC Devices Incorporated - 2K Programmable Line Buffer

Numéro de référence LF9502
Description 2K Programmable Line Buffer
Fabricant LOGIC Devices Incorporated 
Logo LOGIC Devices Incorporated 





1 Page

No Preview Available !





LF9502 fiche technique
DEVICES INCORPORATED
DEVICES INCORPORATED
LF9502
2K ProgrammabLleFLi9ne5B0u2ffer
2K Programmable Line Buffer
FEATURES
DESCRIPTION
u 50 MHz Maximum Operating
Frequency
u Programmable Buffer Length from
2 to 2049 Clock Cycles
u 10-bit Data Inputs and Outputs
u Data Delay and Data Recirculation
Modes
u Supports Positive or Negative Edge
System Clocks
u Expandable Data Word Width or
Buffer Length
u 44-pin PLCC, J-Lead
The LF9502 is a high-speed, 10-bit
programmable line buffer. Some
applications the LF9502 is useful for
include sample rate conversion, data
time compression/expansion, soft-
ware controlled data alignment, and
programmable serial data shifting. By
using the MODSEL pin, two different
modes of operation can be selected:
delay mode and data recirculation
mode. The delay mode provides a
minimum of 2 to a maximum of 2049
clock cycles of delay between the
input and output of the device. The
data recirculation mode provides a
feedback path from the data output to
the data input for use as a program-
mable circular buffer.
By using the length control input
(LC10-0) and the length control enable
(LCEN) the length of the delay buffer
or amount of recirculation delay can
be programmed. Providing a delay
value on the LC10-0 inputs and driving
LCEN LOW will load the delay value
into the length control register on the
next selected clock edge. Two regis-
ters, one preceeding the program-
mable delay RAM and one following,
are included in the delay path. There-
fore, the programmed delay value
should equal the desired delay minus
2. This consequently means that the
value loaded into the length control
register must range from 0 to 2047 (to
provide an overall range of 2 to 2049).
The active edge of the clock input,
either positive or negative edge, can
be selected with the clock select
(CLKSEL) input. All timing is based
on the active clock edge selected by
CLKSEL. Data can be held tempo-
rarily by using the clock enable
(CLKEN) input.
LF9502 BLOCK DIAGRAM
MODSEL
REGISTER
10
DI9-0
10
LCO10-0 LCEN
11
REGISTER
11
10 10
OE
10 10
DO9-0
CLKSEL
CLKEN
CLK
10
TO ALL REGISTERS
Video Imaging Products
1 08/16/2000–LDS.9502-G

PagesPages 7
Télécharger [ LF9502 ]


Fiche technique recommandé

No Description détaillée Fabricant
LF9501 Programmable Line Buffer LOGIC Devices Incorporated
LOGIC Devices Incorporated
LF9501JC20 Programmable Line Buffer LOGIC Devices Incorporated
LOGIC Devices Incorporated
LF9501JC25 Programmable Line Buffer LOGIC Devices Incorporated
LOGIC Devices Incorporated
LF9502 2K Programmable Line Buffer LOGIC Devices Incorporated
LOGIC Devices Incorporated

US18650VTC5A

Lithium-Ion Battery

Sony
Sony
TSPC106

PCI Bus Bridge Memory Controller

ATMEL
ATMEL
TP9380

NPN SILICON RF POWER TRANSISTOR

Advanced Semiconductor
Advanced Semiconductor


www.DataSheetWiki.com    |   2020   |   Contactez-nous  |   Recherche