PDF M13S32321A Data sheet ( Hoja de datos )

Número de pieza	M13S32321A
Descripción	256K x 32 Bit x 4 Banks Double Data Rate SDRAM
Fabricantes	Elite Semiconductor Memory Technology
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No Preview Available ! ESMTwww.DataSheet4U.com DDR SDRAM Features M13S32321A 256K x 32 Bit x 4 Banks Double Data Rate SDRAM z JEDEC Standard z Internal pipelined double-data-rate architecture, two data access per clock cycle z Bi-directional data strobe (DQS) z On-chip DLL z Differential clock inputs (CLK and CLK ) z DLL aligns DQ and DQS transition with CLK transition z Quad bank operation z CAS Latency : 3; 4 z Burst Type : Sequential and Interleave z Burst Length : 2, 4, 8 z All inputs except data & DM are sampled at the rising edge of the system clock(CLK) z Data I/O transitions on both edges of data strobe (DQS) z DQS is edge-aligned with data for reads; center-aligned with data for WRITE z Data mask (DM) for write masking only z VDD = 2.375V ~ 2.625V, VDDQ = 2.375V ~ 2.625V z Auto & Self refresh z 32ms refresh period (4K cycle) z SSTL-2 I/O interface z 100pin LQFP package Operating Frequencies : PRODUCT NO. M13S32321A -5L MAX FREQ 200MHz VDD 2.5V M13S32321A -6L 166MHz 2.5V PACKAGE 100 LQFP 100 LQFP Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2006 Revision : 1.0 1/49 1 page ESMTwww.DataSheet4U.com DC Specifications M13S32321A Parameter Symbol Test Condition Operation Current (One Bank Active) IDD0 Operation Current (One Bank Active) IDD1 Precharge Power-down Standby Current IDD2P tRC = tRC (min) tCK = tCK (min) Active – Precharge Burst Length = 2 tRC = tRC (min), CL= 3 IOUT = 0mA, Active-Read- Precharge CKE ≤ VIL(max), tCK = tCK (min), All banks idle Idle Standby Current IDD2N Active Power-down Current Standby IDD3P Active Standby Current IDD3N Operation Current (Read) Operation Current (Write) Auto Refresh Current Self Refresh Current IDD4R IDD4W IDD5 IDD6 CKE ≥ VIH(min), CS ≥ VIH(min), tCK = tCK (min) All banks ACT, CKE ≤ VIL(max), tCK = tCK (min) One bank; Active-Precharge, tRC = tRAS(max), tCK = tCK (min) Burst Length = 2, CL= 3 , tCK = tCK (min), IOUT = 0mA Burst Length = 2, CL= 3 , tCK = tCK (min) tRC ≥ tRFC(min) CKE ≤ 0.2V Note 1. Enable on-chip refresh and address counters. AC Operation Conditions & Timing Specification Version -5 -6 120 100 175 150 20 20 70 60 20 20 90 80 260 220 210 180 190 160 33 Unit Note mA mA mA mA mA mA mA mA mA mA 1 AC Operation Conditions Parameter Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals Input Different Voltage, CLK and CLK inputs Symbol VIH(AC) VIL(AC) VID(AC) Min VREF + 0.45 0.7 Max VREF - 0.45 VDDQ+0.6 Unit V V V Note 1 Input Crossing Point Voltage, CLK and CLK inputs VIX(AC) 0.5VDDQ-0.2 0.5VDDQ+0.2 V 2 Note1. VID is the magnitude of the difference between the input level on CLK and the input on CLK . 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same. Input / Output Capacitance (VDD = 2.375V, VDDQ =2.5~2.625V, VDDQ =2.375V~2.625V, TA = 25 °C , f = 1MHz) Parameter Input capacitance (A0~A11, BA0~BA1, CKE, CS , RAS , CAS , WE ) Input capacitance (CLK, CLK ) Data & DQS input/output capacitance Input capacitance (DM) Symbol CIN1 CIN2 COUT CIN3 Min Max Unit 2 3 pF 2 3 pF 4.0 5 pF 4.0 5 pF Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2006 Revision : 1.0 5/49 5 Page ESMTwww.DataSheet4U.com M13S32321A Mode Register Definition Mode Register Set (MRS) The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for variety of different applications. The default value of the register is not defined, therefore the mode register must be written after EMRS setting for proper DDR SDRAM operation. The mode register is written by asserting low on CS , RAS , CAS , WE and BA0 (The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the mode register). The state of address pins A0~A11 in the same cycle as CS , RAS , CAS , WE and BA0 going low is written in the mode register. Two clock cycles are requested to complete the write operation in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0~A2, addressing mode uses A3, CAS latency (read latency from column address) uses A4~A6. A7 is used for test mode. A8 is used for DLL reset. A7 must be set to low for normal MRS operation. Refer to the table for specific codes for various burst length, addressing modes and CAS latencies. BA1 BA0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 00 RFU DLL TM CAS Latency BT Burst Length Mode Register BA1 BA0 00 01 A8 DLL Reset 0 No 1 Yes A7 Mode 0 Normal 1 Test A3 Burst Type 0 Sequential 1 Interleave Operating Mode MRS Cycle EMRS Cycle CAS Latency A6 A5 A4 000 001 011 100 101 110 111 Latency Reserve Reserve 3 4 Reserve Reserve Reserve Burst Length A2 A1 A0 000 001 010 011 100 101 110 111 Latency Sequential Interleave Reserve Reserve 22 44 88 Reserve Reserve Reserve Reserve Reserve Reserve Reserve Reserve Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2006 Revision : 1.0 11/49 11 Page

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