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PDF IDTCSPU877A Data sheet ( Hoja de datos )
| Número de pieza | IDTCSPU877A | |
| Descripción | 1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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IDTCSPU877A
1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
www.DataSheet4U.com
1.8V PHASE LOCKED LOOP
DIFFERENTIAL 1:10 SDRAM
CLOCK DRIVER
COMMERCIALTEMPERATURERANGE
IDTCSPU877A
FEATURES:
• 1 to 10 differential clock distribution
• Optimized for clock distribution in DDR2 (Double Data Rate)
SDRAM applications
• Operating frequency: 125MHz to 270MHz
• Very low skew: ≤40ps
• Very low jitter: ≤40ps
• 1.8V AVDD and 1.8V VDDQ
• CMOS control signal input
• Test mode enables buffers while disabling PLL
• Low current power-down mode
• Tolerant of Spread Spectrum input clock
• Available in 52-Ball VFBGA and 40-pin MLF packages
APPLICATIONS:
• Meets or exceeds JEDEC standard 82.8 for registered DDR2
clock driver
• Along with SSTU32864/65/66, DDR2 register, provides complete
solution for DDR2 DIMMs
DESCRIPTION:
The CSPU877A is a PLL based clock driver that acts as a zero delay buffer
to distribute one differential clock input pair(CLK, CLK ) to 10 differential
output pairs (Y [0:9], Y [0:9]) and one differential pair of feedback clock output
(FBOUT, FBOUT). External feedback pins (FBIN, FBIN) for synchronization
of the outputs to the input reference is provided. OE, OS, and AVDD control the
power-down and test mode logic. When AVDD is grounded, the PLL is turned
off and bypassed for test mode purposes. When the differential clock inputs
(CLK, CLK) are both at logic low, this device will enter a low power-down mode.
In this mode, the receivers are disabled, the PLL is turned off, and the output
clock drivers are disabled, resulting in a current consumption device of less than
500µA.
The CSPU877A requires no external components and has been optimised
for very low phase error, skew, and jitter, while maintaining frequency and duty
cycle over the operating voltage and temperature range. The CSPU877A,
designed for use in both module assemblies and system motherboard based
solutions, provides an optimum high-performance clock source.
The CSPU877A is available in Commercial Temperature Range (0°C to
+70°C). See Ordering Information for details.
FUNCTIONAL BLOCK DIAGRAM
OE
OS
AVDD
POWER
DOWN
AND
TEST
MODE
LOGIC
LD
LD or OE
LD, OS, or OE
PLL BYPASS
CLK
CLK
10KΩ - 100KΩ
FBIN
FBIN
PLL
NOTE:
The Logic Detect (LD) powers down the device when a logic LOW is applied to both CLK and CLK.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
c 2004 Integrated Device Technology, Inc.
1
Y0
Y0
Y1
Y1
Y2
Y2
Y3
Y3
Y4
Y4
Y5
Y5
Y6
Y6
Y7
Y7
Y8
Y8
Y9
Y9
FBOUT
FBOUT
JANUARY 2004
DSC-6495/4
1 page  
IDTCSPU877A
1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
www.DataSheet4U.com
COMMERCIALTEMPERATURERANGE
FUNCTION TABLE(1,2)
INPUTS
AVDD OE OS
GND H
X
GND H
X
GND L H
CLK
L
H
L
GND L
L
H
1.8V (nom)
L
H
L
1.8V (nom)
L
L
H
1.8V (nom)
1.8V (nom)
1.8V (nom)
X
H
H
X
X
X
X
X
X
L
H
L(3)
H
OUTPUTS
CLK Y
Y
FBOUT
FBOUT
H LH
L
H
L HL
H
L
H L(z) L(z)
L
H
L(z) L(z)
L Y7 Y7
H
L
Active
Active
H L(z) L(z)
L
H
L(z) L(z)
L Y7 Y7
H
L
Active
Active
H LH
L
H
L HL
H
L(3) L(z) L(z) L(z)
L
L(z)
H Reserved
PLL
OFF
OFF
OFF
OFF
ON
ON
ON
ON
OFF
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
2. L(z) means the outputs are disabled to a LOW state, meeting the IODL limit in DC Electrical Characteristics table.
3. The device will enter a low power-down mode when CLK and CLK are both at logic LOW.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = 0°C to +70°C
Symbol
Parameter
Conditions
Min. Typ. Max. Unit
VIK
VIL(2)
VIH(2)
VIN(1)
VID(DC)(2)
VOD(3)
VOH
Input Clamp Voltage (All Inputs)
Input LOW Voltage (OE, OS, CLK, CLK)
Input HIGH Voltage (OE, OS, CLK, CLK)
Input Signal Voltage
DC Input Differential Voltage
Output Differential Voltage
Output HIGH Voltage
VDDQ = 1.7V, II = -18mA
AVDD/VDDQ = 1.7V
IOH = -100µA, VDDQ = 1.7V to 1.9V
0.65VDDQ
-0.3
0.3
0.5
VDDQ - 0.2
– 1.2
0.35VDDQ
V
V
VDDQ + 0.3 V
VDDQ + 0.4
V
V
V
VOL OutputLOWVoltage
IOH = -9mA, VDDQ = 1.7V
IOL = 100µA, VDDQ = 1.7V to 1.9V
IOL = 9mA, VDDQ = 1.7V
1.1
0.1 V
0.6
IODL Output Disabled LOW Current
IIN InputCurrent CLK, CLK
OE = L, VODL = 100mV, AVDD/VDDQ = 1.7V
AVDD/VDDQ = Max., VI = 0V to VDDQ
100 µA
±250 µA
OE, OS, FBIN, FBIN
±10
IDDLD Static Supply Current (IDDQ and IADD)
AVDD/VDDQ = Max., CLK and CLK = GND
500 µA
IDD Dynamic Power Supply Current
(IDDQ andIADD)(4,5)
AVDD/VDDQ = Max., CLK = 270MHz
300 mA
NOTES:
1. VIN specifies the allowable DC excursion of each different output.
2. VID is the magnitude of the difference between the input level on CLK and the input level on CLK. The CLK and CLK VIH and VIL limits are used to define the DC LOW and HIGH
levels for the power down mode.
3. VOD is the magnitude of the difference between the true output level and the complementary level.
4. All Outputs are left open (unconnected to PCB).
5. Total IDD = IDDQ + IADD = FCK * CPD * VDDQ, for Cpd = (IDDQ + IADD) / (FCK * VDDQ) where FCK is the input frequency, VDDQ is the power supply, and CPD is the Power Dissipation Capacitance.
5
5 Page 
IDTCSPU877A
1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
www.DataSheet4U.com
TEST CIRCUIT AND SWITCHING WAVEFORMS
COMMERCIALTEMPERATURERANGE
80%
Clock Inputs and
Outputs, OE
20%
tR(I), tR(O)
V80% V20%
tSLR(I/O) =
tR(I/O)
80%
20%
tF(I), tF(O)
V80% V20%
tSLF(I/O) =
tF(I/O)
Input and Output Slew Rates
VID, VOD
VIA
CARD
VDDQ
1Ω
GND
VIA
CARD
BEAD
0603
4.7uF
1206
0.1uF
0603
2200pF
0603
AVDD VDDQ
CSPU877A
1
AGND GND
NOTES:
Place all decoupling capacitors as close to the CSPU877A pins as possible.
Use wide traces for AVDD and AGND.
Recommended bead: Fair-rite P/N 2506036017Y0 or equivalent (0.8Ω DC max., 600Ω at 100MHz).
Recommended Filtering for the Analog and Digital Power Supplies (AVDD and VDDQ)
10 0.1uF
0603
APPLICATION INFORMATION
Clock Structure
#1
#2
# of SDRAM Loads per Clock
2
4
Clock Loading on the PLL outputs (pF)
Min. Max.
35
6 10
11
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet IDTCSPU877A.PDF ] | |
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