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PDF IDTCSPT857A Data sheet ( Hoja de datos )
| Número de pieza | IDTCSPT857A | |
| Descripción | 2.5V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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IDTCSPT857/A
2.5V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
www.DataSheet4U.com
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
2.5V PHASE LOCKED LOOP
DIFFERENTIAL 1:10 SDRAM
CLOCK DRIVER
IDTCSPT857/A
FEATURES:
• Optimized for clock distribution in DDR (Double Data Rate)
SDRAM applications
• Operating frequency: 60MHz to 200MHz
• Standard speed: PC1600 (DDR200), PC2100 (DDR266)
• A speed: PC1600 (DDR200), PC2100 (DDR266), PC2700 (DDR333)
• 1 to 10 differential clock distribution
• Very low skew (<100ps)
• Very low jitter (<75ps)
• 2.5V AVDD and 2.5V VDDQ
• CMOS control signal input
• Test mode enables buffers while disabling PLL
• Low current power-down mode
• Tolerant of Spread Spectrum input clock
• Available in 48-pin TSSOP and 56-pin VFBGA packages
DESCRIPTION:
The CSPT857 is a PLL based clock driver that acts as a zero delay buffer
to distribute one differential clock input pair(CLK, CLK ) to 10 differential output
pairs (Y[0:9],Y[0:9]) and one differential pair of feedback clock output (FBOUT,
FBOUT). External feedback pins (FBIN, FBIN) for synchronization of the
outputs to the input reference is provided. A CMOS Enable/Disable pin is
available for low power disable. When the output frequency falls below
approximately 20MHz, the device will enter power down mode. In this mode,
the receivers are disabled, the PLL is turned off, and the output clock drivers
are tristated, resulting in a current consumption device of less than 200µA.
The CSPT857 requires no external components and has been optimised
for very low I/O phase error, skew, and jitter, while maintaining frequency and
duty cycle over the operating voltage and temperature range. The CSPT857,
designed for use in both module assemblies and system motherboard based
solutions, provides an optimum high-performance clock source.
The CSPT857 is only available in Industrial Temperature Range (-40°C to
+85°C), and CSPT857A is only available in Commercial Temperature Range
(0°C to +70°C). See Ordering Information for details.
FUNCTIONAL BLOCK DIAGRAM
37/E6
PWRDWN
AVDD 16/G2
TEST
MODE
LOGIC
CLK
CLK
13/F1
14/F2
FBIN
FBIN
36/F6
35/F5
PLL
3/A1
2/A2
5/B2
6/B1
10/D1
9/D2
20/J2
19/J1
22/K1
23/K2
46/A6
47/A5
44/B5
43/B6
39/D6
40/D5
29/J5
30/J6
Y0
Y0
Y1
Y1
Y2
Y2
Y3
Y3
Y4
Y4
Y5
Y5
Y6
Y6
Y7
Y7
Y8
Y8
27/K6
26/K5
Y9
Y9
32/H6
33/H5
FBOUT
FBOUT
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL
c 2002 Integrated Device Technology, Inc.
TEMPERATURE
1
RANGES
OCTOBER 2002
DSC-5172/8
1 page  
IDTCSPT857/A
2.5V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
www.DataSheet4U.com
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = 0°C to +70°C; Industrial: TA = –40°C to +85°C
Symbol Parameter
Conditions
Min. Typ. Max. Unit
VIK
VIL (dc)
VIH (dc)
VIL (ac)
VIH (ac)
VOL
VOH
VIX
VID(DC)(1)
VID(AC)(1)
IIN
IDDPD
IDDQ
IADD
Input Clamp Voltage (All Inputs)
Static Input LOW Voltage
Static Input HIGH Voltage
Dynamic Input LOW Voltage
Dynamic Input HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
Input Differential Cross Voltage
DC Input Differential Voltage
AC Input Differential Voltage
Input Current
Power-Down Current on VDDQ and AVDD
Dynamic Power Supply Current on VDDQ
Dynamic Power Supply Current on AVDD
VDDQ = 2.3V, II = -18mA
PWRDWN
PWRDWN
CLK, CLK, FBIN, FBIN
CLK, CLK, FBIN, FBIN
AVDD/VDDQ = Min., IOL = 100µA
AVDD/VDDQ = Min., IOL = 12mA
AVDD/VDDQ = Min., IOH = -100µA
AVDD/VDDQ = Min., IOH = -12mA
VDDQ = 2.7V, VI = 0V to 2.7V
AVDD/VDDQ = Max., CLK = 0MHz or PWRDWN = L
AVDD/VDDQ = Max., CLK = 200MHz, 120Ω/14pF
AVDD/VDDQ = Max., CLK = 170MHz, 120Ω/14pF
AVDD/VDDQ = Max., CLK = 170MHz
– 0.3
1.7
1.7
VDDQ – 0.1
1.7
VDDQ/2 – 0.2
0.36
0.7
– 1.2 V
0.7 V
VDDQ + 0.3
0.7 V
VDDQ
0.1 V
0.6
V
VDDQ/2 + 0.2 V
VDDQ + 0.6 V
VDDQ + 0.6 V
±10 µA
100 200 µA
320 360 mA
250 300
12 mA
NOTE:
1. VID is the magnitude of the difference between the input level on CLK and the input level on CLK.
5
5 Page 
IDTCSPT857/A
2.5V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
www.DataSheet4U.com
APPLICATION INFORMATION
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
~2.5"
~0.6" (split to terminator)
CLK
C = 14pF
CLK
(1)
C = 14pF
CSPT857/A
R = 120Ω
FBIN
R = 120Ω
FBIN
Z = 60Ω
Z = 60Ω
8 more
~0.3"
SDRAM
R = 120Ω
SDRAM
Feedback path
Figure 9. Clock Structure 1
CLK
C = 14pF
CLK
(1)
C = 14pF
CSPT857/A
R = 120Ω
FBIN
R = 120Ω
FBIN
~2.5"
Z = 60Ω
Z = 60Ω
~0.6" (split to terminator)
SDRAM
SDRAM
Stacked
R = 120Ω
8 more
~0.3"
SDRAM
SDRAM
Stacked
Feedback path
Figure 10. Clock Structure 2
NOTE:
1. Memory module vendors may need to adjust the feedback capacitive load in order to meet DDR SDRAM registered DIMM timing requirements.
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet IDTCSPT857A.PDF ] | |
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