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PDF SM5951A Data sheet ( Hoja de datos )
| Número de pieza | SM5951A | |
| Descripción | 8-channel DSD Editing System Signal Processor LSI | |
| Fabricantes | NPC | |
| Logotipo |  |
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SM5951A
8-channel DSD Editing System Signal Processor LSI
OVERVIEW
The SM5951A is an 8-channel DSD (Direct Stream Digital) editing system signal processor LSI. It takes 4
DSD input signals per channel, mixes them, and then converts the result back into 1-bit DSD data for output.
FEATURES
I DSD signal sampling rate: 5.6448MHz (128 × 44.1kHz) and 2.8224MHz (64 × 44.1kHz) supported
I 8-channel DSD signal mixing
• 8-channel, 4 DSD signal inputs per channel mixing using arbitrary coefficients for each input
I Raw signal switching function (auto bypass)
• Automatically switches to raw signal output with no switching noise and no signal degradation when mix-
ing is not required, bypassing the mixing processing
I Input/output format
• Normal input/output format where the data changes are synchronized to the bit clock cycle, and Manches-
ter-type encoding input/output format where the data inverts during the bit clock cycle
I Monitor output: Simultaneous 64 × 44.1kHz monitor data output when in 128 × 44.1kHz sampling rate mode
I Microcontroller interface: Parallel bi-directional 8-bit/16-bit/32-bit data bus supported
I Master clock: 45.1584MHz (1024 × 44.1kHz) or 56.448MHz (1280 × 44.1kHz)
I 2 voltage supplies: 3.3V (3.0 to 3.6V) and 2.5V (2.3 to 2.7V)
I Operating temperature range: − 20 to 70°C
I Package: 160-pin QFP
PACKAGE DIMENSIONS
(Unit: mm)
31.2 ± 0.4
28.0 ± 0.1
0.11 to 0.23
0.22 to 0.4
0.65
15
1.6
0.15 0.8
15 0.8 ± 0.2
ORDERING INFORMATION
Device
SM5951AF
Package
160-pin QFP
0 to 10.0
SEIKO NPC CORPORATION —1
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SM5951A
PIN DESCRIPTION
Number of
Pins
Name
I/O
Polarity1
Voltage
Functional Description
1 RST_X I
PU, S
3.3V System Reset
1 FS
I
− 3.3V 1fs Clock (44.1kHz)
1 CLK I
− 3.3V Master Clock
1 SEL1280 I
PD, S
3.3V
Select Master Clock Rate
[HIGH]: 1280 × 44.1kHz, [LOW]: 1024 × 44.1kHz
1 SELDSDI I
PD, S
3.3V
Select DSD Input Format
[HIGH]: Manchester Encoding, [LOW]: Normal
1 SELDSDO I
PD, S
3.3V
Select DSD Output Format
[HIGH]: Manchester Encoding, [LOW]: Normal
2 SELBUS [1:0]
I
PU, S
Select MCU Data Bus Width
[SELBUS1, SELBUS0]
3.3V [LOW, LOW]: 8-bit
[LOW, HIGH]: 16-bit
[HIGH, × (LOW or HIGH)]: 32-bit
1 CS_X I
PU 3.3V MCU I/F: Chip Select
1 WR_X
I
PU, S
3.3V MCU I/F: Write Enable
1 RD_X
I
PU, S
3.3V MCU I/F: Read Enable
8 ADDR [7:0]
I
PU 3.3V MCU I/F: Address Bus
32 DATA [31:0] I/O
3mA
3.3V MCU I/F: Data Bus
1 BCKI I
S 3.3V DSD Input: Bit Clock IN
4 DSDI1_[3:0] I
− 3.3V DSD Input: DSD CH1 Data (LINE0 to LINE3)
4 DSDI2_[3:0] I
− 3.3V DSD Input: DSD CH2 Data (LINE0 to LINE3)
4 DSDI3_[3:0] I
− 3.3V DSD Input: DSD CH3 Data (LINE0 to LINE3)
4 DSDI4_[3:0] I
− 3.3V DSD Input: DSD CH4 Data (LINE0 to LINE3)
4 DSDI5_[3:0] I
− 3.3V DSD Input: DSD CH5 Data (LINE0 to LINE3)
4 DSDI6_[3:0] I
− 3.3V DSD Input: DSD CH6 Data (LINE0 to LINE3)
4 DSDI7_[3:0] I
− 3.3V DSD Input: DSD CH7 Data (LINE0 to LINE3)
4 DSDI8_[3:0] I
− 3.3V DSD Input: DSD CH8 Data (LINE0 to LINE3)
1 EXMUTE I
− 3.3V DSD Input: External Mute Pattern
1 BCKO O 6mA 3.3V DSD Output: Bit Clock Out
8 DSDO [8:1] O 3mA 3.3V DSD Output: DSD Output DATA (CH1 to CH8)
1 BCK64O O 6mA 3.3V DSD 64fs Output: Bit Clock Out
8 DSD64O [8:1] O 3mA 3.3V DSD 64fs Output: DSD Output DATA (CH1 to CH8)
1 MOSYNC O 3mA 3.3V SYNC Monitor
8 TEST [8:1] I
PD 3.3V IOTEST_EN, SCAN_EN, ATPG_EN, FUNC_MODE etc.
10 VDDH − − 3.3V Power Supply (I/O)
14 VDDL − − 2.5V Power Supply (Core)
24 VSS −
−
0V Ground Level
1. Attributes: S = Schmitt type, PU = with pull-up resistor, PD = with pull-down resistor, mA = output current
SEIKO NPC CORPORATION —5
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SM5951A
DSD output format
The DSD output format can be set to one of 2 types by the state of SELDSDO.
(1) Normal mode (SELDSDO = LOW)
DSD output data transitions occur on the falling edge of the bit clock BCKO.
BCKO
BCK64O
DSDO*
DSD64O*
(1/64fs or 1/128fs)
D1
D2
(2) Manchester-type output (SELDSDO = HIGH)
DSD output data transitions occur on the falling edge of the bit clock BCKO and then inverts on the rising
edge of the bit clock BCKO.
BCKO
BCK64O
(1/64fs or 1/128fs)
DSDO*
DSD64O*
D1 D1 D2 D2
Note. DSDO*: DSDO [8:1] pins, DSD64O*: DSD64O [8:1] pins
MCU Interface
Bus access control
The internal mode and coefficients can be set using either 8/16/32-bit data bus, facilitating easy connection to
various kinds of MCU bus.
The data bus control pins are active LOW. When the chip select (CS_X) is active, read/write control inputs are
valid. When write control (WR_X) is active, data is written in on the rising edge. Data is read out when the read
control (RD_X) is active.
ADDR [7:0]
<Data Read>
<Data Write>
CS_X
RD_X
WR_X
DATA [31:0] (Out)
Hi-Z
Data (Out)
Hi-Z
DATA [31:0] (In)
Hi-Z
Data (In)
Note. DATA [31:0] pins have an additional bus hold circuit which holds the previous data even when the pin is in a high-impedance ("Hi-Z") state.
SEIKO NPC CORPORATION —11
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