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PDF LM20333A Data sheet ( Hoja de datos )
| Número de pieza | LM20333A | |
| Descripción | 3A Synchronous Buck Regulator | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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www.DataSheet4U.com
January 20, 2009
LM20333A
36V, 3A Synchronous Buck Regulator with Frequency
Synchronization
General Description
The LM20333A is a full featured synchronous buck regulator
capable of delivering up to 3A of load current. The current
mode control loop is externally compensated with only two
components, offering both high performance and ease of use.
The device is optimized to work over the input voltage range
of 4.5V to 36V making it well suited for high voltage systems.
The device features internal Over Voltage Protection (OVP)
and Over Current Protection (OCP) circuits for increased sys-
tem reliability. A precision Enable pin and integrated UVLO
allows the turn on of the device to be tightly controlled and
sequenced. Startup inrush currents are limited by both an in-
ternally fixed and externally adjustable soft-start circuit. Fault
detection and supply sequencing are possible with the inte-
grated power good (PGOOD) circuit.
The LM20333A is designed to work well in multi-rail power
supply architectures. The output voltage of the device can be
configured to track a higher voltage rail using the SS/TRK pin.
If the output of the LM20333A is pre-biased at startup it will
not sink current to pull the output low until the internal soft-
start ramp exceeds the voltage at the feedback pin.
The switching frequency of the LM20333A can be synchro-
nized to an external clock by use of the SYNC pin. The SYNC
pin is capable of synchronizing to input signals ranging from
250 kHz to 1.5 MHz.
The LM20333A is offered in an exposed pad 20-pin eTSSOP
package that can be soldered to the PCB, eliminating the
need for bulky heatsinks.
Features
■ 4.5V to 36V input voltage range
■ 3A output current, 5.2A peak current
■ 130 mΩ/110 mΩ integrated power MOSFETs
■ 94% peak efficiency with synchronous rectification
■ 1.0% feedback voltage accuracy
■ Current mode control, selectable compensation
■ Oscillator synchronization from 250kHz to 1.5MHz
■ Adjustable output voltage down to 0.8V
■ Compatible with pre-biased loads
■ Programmable soft-start with external capacitor
■ Precision enable pin with hysteresis
■ OVP, UVLO inputs and PGOOD output
■ Internally protected with peak current limit, thermal
shutdown and restart
■ Accurate current limit minimizes inductor size
■ Non-linear current mode slope compensation
■ eTSSOP-20 exposed pad package
Applications
■ Simple to design, high efficiency point of load regulation
from a 4.5V to 36V bus
■ High Performance DSPs, FPGAs, ASICs and
Microprocessors
■ Communications Infrastructure, Automotive
Simplified Application Circuit
PowerWise® is a registered trademark of National Semiconductor Corporation.
© 2009 National Semiconductor Corporation 300774
30077401
www.national.com
1 page  
Symbol Parameter
www.DgamtaSheet4EUr.rcoormAmplifier DC Transconductance
AVOL
Error Amplifier Voltage Gain
GBW
Error Amplifier Gain-Bandwidth Product
Current Limit
ILIM
ILIMNEG
TILIM
Enable
Cycle By Cycle Positive Current Limit
Cycle By Cycle Negative Current Limit
Cycle By Cycle Current Limit Delay
VEN(RISING) EN Pin Rising Threshold
VEN(HYS) EN Pin Hysteresis
IEN EN Source Current
Thermal Shutdown
TSD Thermal Shutdown
TSD(HYS) Thermal Shutdown Hysteresis
Thermal Resistance
θJC Junction to Case
θJA Junction to Ambient (Note 3)
Conditions
ICOMP = -50 µA to +50 µA
COMP pin open
COMP pin open
VEN = 0V, VVIN = 12V
0 LFM airflow
Min Typ Max Units
450 515 600 µmho
2000
V/V
7 MHz
4.3 5.2 6.0 A
2.8 A
150 ns
1.2 1.25 1.3 V
50 mV
2 µA
170 °C
20 °C
5.6 °C/W
27 °C/W
Note 1: Absolute Maximum Ratings indicate limits beyond witch damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics.
Note 2: The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor to each pin.
Note 3: Measured on a 4 layer 2" x 2" PCB with 1 oz. copper weight inner layers and 2 oz. outer layers.
Typical Performance Characteristics Unless otherwise specified: VVIN = 12V, VOUT = 3.3V, L= 4.7µH,
fSW=750kHz, CSS = 100nF, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others.
Efficiency vs. Load Current
fSW = 350 kHz
Efficiency vs. Load Current
fSW = 500 kHz
30077403
5
30077404
www.national.com
5 Page 
wwOwp.DeatarSahteieot4nU.cDomescription
GENERAL
The LM20333A switching regulator features all of the func-
tions necessary to implement an efficient buck regulator using
a minimum number of external components. This easy to use
regulator features two integrated switches and is capable of
supplying up to 3A of continuous output current. The regulator
utilizes peak current mode control with nonlinear slope com-
pensation to optimize stability and transient response over the
entire output voltage range. Peak current mode control also
provides inherent line feed-forward, cycle-by-cycle current
limiting and easy loop compensation. The switching frequen-
cy can be synchronized to an external oscillator over the
range of 250 kHz to 1.5 MHz. The SYNC function allows the
device to operate at high switching frequencies minimizing
the size of the inductor while still achieving efficiencies as high
as 94%. The precision internal voltage reference allows the
output to be set as low as 0.8V. Fault protection features in-
clude: current limiting, thermal shutdown, over voltage pro-
tection, and shutdown capability. The device is available in
the eTSSOP-20 package featuring an exposed pad to aid
thermal dissipation. The typical application circuit for the
LM20333A is shown in Figure 1 in the design guide.
PRECISION ENABLE
The enable (EN) pin allows the output of the device to be en-
abled or disabled with an external control signal. This pin is a
precision analog input that enables the device when the volt-
age exceeds 1.25V (typical). The EN pin has 50 mV of hys-
teresis and will disable the output when the enable voltage
falls below 1.2V (typical). If the EN pin is not used, it should
be disconnected so the internal 2 µA pull-up will default this
function to the enabled condition. Since the enable pin has a
precise turn-on threshold it can be used along with an external
resistor divider network from VIN to configure the device to
turn-on at a precise input voltage. The precision enable cir-
cuitry will remain active even when the device is disabled.
FREQUENCY SYNCHRONIZATION
The frequency sychronization pin(SYNC) allows the switching
frequency of the device to be controlled with an external clock
signal. This feature allows the user to sychronize multiple
converters, avoiding undesirable frequency bands of opera-
tion.
The switching frequency of the device will synchronize to the
rising edge of the clock source that is driving the SYNC pin.
The logic low level for the input clock must be below 0.8V and
the logic high level must exceed 2.0V to guarantee proper
operation. The device will synchronize to frequencies from
250 kHz to 1.5 MHz. If the synchronization clock is removed
or not present during startup, the oscillator of the device will
run at approximately 200 kHz. If the SYNC pin is not used it
should be connected to ground.
PEAK CURRENT MODE CONTROL
In most cases, the peak current mode control architecture
used in the LM20333A only requires two external components
to achieve a stable design. The compensation can be select-
ed to accommodate any capacitor type or value. The external
compensation also allows the user to set the crossover fre-
quency and optimize the transient performance of the device.
For duty cycles above 50% all peak current mode control buck
converters require the addition of an artificial ramp to avoid
sub-harmonic oscillation. This artificial linear ramp is com-
monly referred to as slope compensation. What makes the
LM20333A unique is the amount of slope compensation will
change depending on the output voltage. When operating at
high output voltages the device will have more slope com-
pensation than when operating at lower output voltages. This
is accomplished in the LM20333A by using a non-linear
parabolic ramp for the slope compensation. The parabolic
slope compensation of the LM20333A is an improvement
over the traditional linear slope compensation because it op-
timizes the stability of the device over the entire output voltage
range.
CURRENT LIMIT
The precise current limit enables the device to operate with
smaller inductors that have lower saturation currents. When
the peak inductor current reaches the current limit threshold,
an over current event is triggered and the internal high-side
FET turns off and the low-side FET turns on, allowing the in-
ductor current to ramp down until the next switching cycle. For
each sequential over-current event, the reference voltage is
decremented and PWM pulses are skipped resulting in a cur-
rent limit that does not aggressively fold back for brief over-
current events, while at the same time providing frequency
and voltage foldback protection during hard short circuit con-
ditions.
SOFT-START AND VOLTAGE TRACKING
The SS/TRK pin is a dual function pin that can be used to set
the startup time or track an external voltage source. The start-
up or soft-start time can be adjusted by connecting a capacitor
from the SS/TRK pin to ground. The soft-start feature allows
the regulator output to gradually reach the steady state oper-
ating point, thus reducing stresses on the input supply and
controlling startup current. If no soft-start capacitor is used the
device defaults to the internal soft-start circuitry resulting in a
startup time of approximately 1 ms. For applications that re-
quire a monotonic startup or utilize the PGOOD pin, an ex-
ternal soft-start capacitor is recommended. The SS/TRK pin
can also be set to track an external voltage source. The track-
ing behavior can be adjusted by two external resistors con-
nected to the SS/TRK pin as shown in Figure 6 in the design
guide.
PRE-BIAS STARTUP CAPABILITY
The LM20333A is in a pre-biased state when it starts up with
an output voltage greater than zero. This often occurs in many
multi-rail applications such as when powering an FPGA,
ASIC, or DSP. In these applications the output can be pre-
biased through parasitic conduction paths from one supply
rail to another. Even though the LM20333A is a synchronous
converter, it will not pull the output low when a pre-bias con-
dition exists. During start up the LM20333A will not sink
current until the soft-start voltage exceeds the voltage on the
FB pin. Since the device cannot sink current, it protects the
load from damage that might otherwise occur if current is
conducted through the parasitic paths of the load.
POWER GOOD AND OVER VOLTAGE FAULT HANDLING
The LM20333A has built in under and over voltage compara-
tors that control the power switches. Whenever there is an
excursion in output voltage above the set OVP threshold, the
part will terminate the present on-pulse, turn-on the low-side
FET, and pull the PGOOD pin low. The low-side FET will re-
main on until either the FB voltage falls back into regulation
or the negative current limit is triggered which in turn tri-states
the FETs. If the output reaches the UVP threshold the part will
continue switching and the PGOOD pin will be deasserted
and go low. Typical values for the PGOOD resistor are on the
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| PDF Descargar | [ Datasheet LM20333A.PDF ] | |
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