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PDF ADC16DV160 Data sheet ( Hoja de datos )
| Número de pieza | ADC16DV160 | |
| Descripción | 160 MSPS Analog-to-Digital Converter | |
| Fabricantes | National Semiconductor | |
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ADC16DV160
PRELIMINARY
August 17, 2009
Dual Channel, 16-Bit, 160 MSPS Analog-to-Digital
Converter with DDR LVDS Outputs
General Description
The ADC16DV160 is a monolithic dual channel high perfor-
mance CMOS analog-to-digital converter capable of convert-
ing analog input signals into 16-bit digital words at rates up to
160 Mega Samples Per Second (MSPS). This converter uses
a differential, pipelined architecture with digital error correc-
tion and an on-chip sample-and-hold circuit to minimize pow-
er consumption and external component count while provid-
ing excellent dynamic performance. Automatic power-up
calibration enables excellent dynamic performance and re-
duces part-to-part variation, and the ADC16DV160 can be re-
calibrated at any time through the 3-wire Serial Peripheral
Interface (SPI). An integrated low noise and stable voltage
reference and differential reference buffer amplifier eases
board level design. The on-chip duty cycle stabilizer with low
additive jitter allows a wide range of input clock duty cycles
without compromising dynamic performance. A unique sam-
ple-and-hold stage yields a full-power bandwidth of 1.4 GHz.
The interface between the ADC16DV160 and a receiver block
can be easily verified and optimized via fixed pattern gener-
ation and output clock position features. The digital data is
provided via dual data rate LVDS outputs – making possible
the 68-pin, 10 mm x 10 mm LLP package. The ADC16DV160
operates on dual power supplies of +1.8V and +3.0V with a
power-down feature to reduce power consumption to very low
levels while allowing fast recovery to full operation.
■ On-chip low jitter duty-cycle stabilizer
■ Power-down and sleep modes
■ Output fixed pattern generation
■ Output clock position adjustment
■ 3-wire SPI
■ Offset binary or 2's complement data format
■ 68-pin LLP package (10x10x0.8, 0.5mm pin-pitch)
Key Specifications
■ Resolution
■ Conversion Rate
■ SNR
(@FIN = 30 MHz)
(@FIN = 197 MHz)
■ SFDR
(@FIN = 30 MHz)
(@FIN = 197 MHz)
■ Full Power Bandwidth
■ Power Consumption
-Core per channel
-LVDS Driver
-Total
■ Operating Temperature Range
16 Bits
160 MSPS
78.5 dBFS (typ)
76.3 dBFS (typ)
95 dBFS (typ)
91.2 dBFS (typ)
1.4 GHz (typ)
591 mW (typ)
118 mW (typ)
1.3W (typ)
-40°C ~ 85°C
Features
■ Low power consumption
■ On-chip precision reference and sample-and-hold circuit
■ On-chip automatic calibration during power-up
■ Dual data rate LVDS output port
■ Dual Supplies: 1.8V and 3.0V operation
■ Selectable input range: 2.4, 2.0, 1.5 and 1.0VPP
■ Sampling edge flipping with clock divider by 2 option
■ Integer clock divider by 1 or 2
Applications
■ Multi-carrier, Multi-standard Base Station Receivers
-MC-GSM/EDGE, CDMA2000, UMTS, LTE and WiMAX
■ High IF Sampling Receivers
■ Diversity Channel Receivers
■ Test and Measurement Equipment
■ Communications Instrumentation
■ Portable Instrumentation
© 2009 National Semiconductor Corporation 301014
www.national.com
1 page  
Pin(s)
Name
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D1/0+/-Q to
28 - 43
D15/14+/-Q
61 - 46
D1/0+/-I to
D15/14+/-I
44 45
OUTCLK+/-
POWER SUPPLIES
4, 14, 22, 64
VA3.0
1 17
VA1.8
0, 3, 15, 18, 21,
65, 68
AGND
62 VDR
63 DRGND
Type
Output
Output
Function and Connection
LVDS Data Output. The 16-bit digital output of the data converter is
provided on these ports in a dual data rate manner. A 100Ω termination
resistor must be placed between each pair of differential signals at the
far end of the transmission line. The odd bit data is output first and should
be captured first when de-interleaving the data.
Output Clock. This pin is used to clock the output data. It has the same
frequency as the sampling clock. One word of data is output in each
cycle of this signal. A 100Ω termination resistor must be placed between
the differential clock signals at the far end of the transmission line. The
falling edge of this signal should be used to capture the odd bit data
(D15, D13, D11…D1). The rising edge of this signal should be used to
capture the even bit data (D14, D12, D10…D0).
Analog Power
Analog Power
Analog Ground
Analog Power
Ground
3.0V Analog Power Supply. These pins should be connected to a quiet
source and should be decoupled to AGND with 0.1 µF capacitors
located close to the power pins.
3.0V Analog Power Supply. These pins should be connected to a quiet
source and should be decoupled to AGND with 0.1 µF capacitors
located close to the power pins.
Analog Ground Return.
Pin 0 is the exposed pad on the bottom of the package. The exposed
pad must be connected to the ground plane to ensure rated
performance.
Output Driver Power Supply. This pin should be connected to a quiet
voltage source and be decoupled to DRGND with a 0.1 µF capacitor
close to the power pins.
Output Driver Ground Return.
5 www.national.com
5 Page 
wwSwp.DeatcaSihfieceta4Ut.icoomn Definitions
APERTURE DELAY is the time after the falling edge of the
clock to when the input signal is acquired or held for conver-
sion.
APERTURE JITTER (APERTURE UNCERTAINTY) is the
variation in aperture delay from sample to sample. Aperture
jitter manifests itself as noise in the output.
CLOCK DUTY CYCLE is the ratio of the time during one cycle
that a repetitive digital waveform is high to the total time of
one period. The specification here refers to the ADC clock
input signal.
COMMON MODE VOLTAGE (VCM) is the common DC volt-
age applied to both input terminals of the ADC.
CONVERSION LATENCY is the number of clock cycles be-
tween initiation of conversion and the time when data is
presented to the output driver stage. Data for any given sam-
ple is available at the output pins the Pipeline Delay plus the
Output Delay after the sample is taken. New data is available
at every clock cycle, but the data lags the conversion by the
pipeline delay.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of
the maximum deviation from the ideal step size of 1 LSB.
FULL POWER BANDWIDTH is a measure of the frequency
at which the reconstructed output fundamental drops 3 dB
below its low frequency value for a full scale input.
GAIN ERROR is the deviation from the ideal slope of the
transfer function. It can be calculated as:
Gain Error = Positive Full Scale Error − Negative Full Scale
Error
It can also be expressed as Positive Gain Error and Negative
Gain Error, which are calculated as:
PGE = Positive Full Scale Error - Offset Error
NGE = Offset Error - Negative Full Scale Error
INTEGRAL NON LINEARITY (INL) is a measure of the de-
viation of each individual code from a best fit straight line. The
deviation of any given code from this straight line is measured
from the center of that code value.
INTERMODULATION DISTORTION (IMD) is the creation of
additional spectral components as a result of two sinusoidal
frequencies being applied to the ADC input at the same time.
It is defined as the ratio of the power in the intermodulation
products to the total power in the original frequencies. IMD is
usually expressed in dBFS.
LSB (LEAST SIGNIFICANT BIT) is the bit that has the small-
est value or weight of all bits. This value is VFS/2n, where
“VFS” is the full scale input voltage and “n” is the ADC reso-
lution in bits.
MISSING CODES are those output codes that will never ap-
pear at the ADC outputs. The ADC16DV160 is guaranteed
not to have any missing codes.
MSB (MOST SIGNIFICANT BIT) is the bit that has the largest
value or weight. Its value is one half of full scale.
NEGATIVE FULL SCALE ERROR is the difference between
the actual first code transition and its ideal value of ½ LSB
above negative full scale.
OFFSET ERROR is the difference between the two input
voltages (VIN+ – VIN-) required to cause a transition from code
32767LSB and 32768LSB with offset binary data format.
PIPELINE DELAY (LATENCY) See CONVERSION LATEN-
CY.
POSITIVE FULL SCALE ERROR is the difference between
the actual last code transition and its ideal value of 1½ LSB
below positive full scale.
POWER SUPPLY REJECTION RATIO is a measure of how
well the ADC rejects a change in the power supply voltage.
PSRR is the ratio of the Full-Scale output of the ADC with the
supply at the minimum DC supply limit to the Full-Scale output
of the ADC with the supply at the maximum DC supply limit,
expressed in dB.
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in
dB, of the power of input signal to the total power of all other
spectral components below one-half the sampling frequency,
not including harmonics and DC.
SIGNAL TO NOISE AND DISTORTION (SINAD) Is the ratio,
expressed in dB, of the power of the input signal to the total
power of all of the other spectral components below half the
clock frequency, including harmonics but excluding DC.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the differ-
ence, expressed in dB, between the power of input signal and
the peak spurious signal power, where a spurious signal is
any signal present in the output spectrum that is not present
at the input.
TOTAL HARMONIC DISTORTION (THD) is the ratio, ex-
pressed in dB, of the total power of the first seven harmonic
to the input signal power. THD is calculated as:
where f12 is the power of the fundamental frequency and f22
through f102 are the powers of the first nine harmonics in the
output spectrum.
SECOND HARMONIC DISTORTION (2ND HARM or H2) is
the difference expressed in dB, from the power of its 2nd har-
monic level to the power of the input signal.
THIRD HARMONIC DISTORTION (3RD HARM or H3) is the
difference expressed in dB, from the power of the 3rd har-
monic level to the power of the input signal.
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| PDF Descargar | [ Datasheet ADC16DV160.PDF ] | |
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