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PDF MAX1438B Data sheet ( Hoja de datos )
| Número de pieza | MAX1438B | |
| Descripción | 1.8V ADC | |
| Fabricantes | Maxim Integrated Products | |
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19-4630; Rev 0; 7/09
www.DataSheet4U.com
EVAALVUAAILTAIOBNLEKIT
Octal, 12-Bit, 64Msps, 1.8V ADC
with Serial LVDS Outputs
General Description
The MAX1438B octal, 12-bit analog-to-digital converter
(ADC) features fully differential inputs, a pipelined
architecture, and digital error correction incorporating a
fully differential signal path. This ADC is optimized for
low-power and high-dynamic performance in medical
imaging instrumentation and digital communications
applications. The MAX1438B operates from a 1.8V sin-
gle supply and consumes only 913mW (114mW per
channel) while delivering a 69.9dB (typ) signal-to-noise
ratio (SNR) at a 5.3MHz input frequency. In addition to
low operating power, the MAX1438B features a low-
power standby mode for idle periods.
An internal 1.24V precision bandgap reference sets the
full-scale range of the ADC. A flexible reference struc-
ture allows the use of an external reference for applica-
tions requiring increased accuracy or a different input
voltage range. The reference architecture is optimized
for low noise.
A single-ended clock controls the data-conversion
process. An internal duty-cycle equalizer compensates
for wide variations in clock duty cycle. An on-chip
phase-locked loop (PLL) generates the high-speed ser-
ial low-voltage differential signal (LVDS) clock.
The MAX1438B has self-aligned serial LVDS outputs for
data, clock, and frame-alignment signals. The output
data is presented in two’s-complement format.
The MAX1438B offers a maximum sample rate of
64Msps. This device is available in a small, 10mm x
10mm x 0.8mm, 68-pin thin QFN package with exposed
pad and is specified for the extended industrial (-40°C
to +85°C) temperature range.
Applications
Ultrasound and Medical Imaging
Instrumentation
Multichannel Communications
Features
♦ Excellent Dynamic Performance
69.9dB SNR at 5.3MHz
94dBc SFDR at 5.3MHz
♦ Ultra-Low Power
114mW per Channel (Normal Operation)
♦ Serial LVDS Outputs
♦ Pin-Selectable LVDS/SLVS (Scalable Low-Voltage
Signal) Mode
♦ LVDS Outputs Support Up to 30in FR4 Backplane
Connections
♦ Test Mode for Digital Signal Integrity
♦ Fully Differential Analog Inputs
♦ Wide Differential Input Voltage Range (1.4VP-P)
♦ On-Chip 1.24V Precision Bandgap Reference
♦ Clock Duty-Cycle Equalizer
♦ Compact, 68-Pin Thin QFN Package with Exposed
Pad
♦ Evaluation Kit Available (Order MAX1437BEVKIT)
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX1438BETK+ -40°C to +85°C
68 Thin QFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1 page  
www.DataSheet4U.com
Octal, 12-Bit, 64Msps, 1.8V ADC
with Serial LVDS Outputs
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = 1.8V, VOVDD = 1.8V, VCVDD = 1.8V, VGND = 0V, external VREFIO = 1.24V, CREFIO to GND = 0.1µF || 1.0µF, CREFP to GND =
10µF, CREFN to GND = 10µF, fCLK = 64MHz (50% duty cycle), DT = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are
at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
TIMING CHARACTERISTICS (Note 5)
CONDITIONS
Data Valid to CLKOUT Rise/Fall
tOD Figure 5 (Note 6)
CLKOUT Output-Width High
CLKOUT Output-Width Low
tCH Figure 5
tCL Figure 5
FRAME Rise to CLKOUT Rise
tCF Figure 4 (Note 6)
MIN TYP MAX UNITS
(tSAMPLE/24)
- 0.15
(tSAMPLE/24)
+ 0.15
tSAMPLE/12
tSAMPLE/12
(tSAMPLE/24)
- 0.15
(tSAMPLE/24)
+ 0.15
ns
ns
ns
ns
Sample CLK Rise to FRAME Rise
tSF Figure 4 (Note 6)
(tSAMPLE/2)
+ 1.1
(tSAMPLE/2)
+ 2.6
ns
Crosstalk
(Note 2)
-73 dB
Gain Matching
Phase Matching
CGM
CPM
fIN = 5.3MHz (Note 2)
fIN = 5.3MHz (Note 2)
±0.1
±0.25
dB
Degrees
Note 1: Specifications at TA ≥ +25°C are guaranteed by production testing. Specifications at TA < +25°C are guaranteed by design
and characterization and not subject to production testing.
Note 2: See definition in the Parameter Definitions section at the end of this data sheet.
Note 3: See the Common-Mode Output (CMOUT) section.
Note 4: Connect REFADJ to GND directly to enable internal reference mode. Connect REFADJ to AVDD directly to disable the internal
bandgap reference and enable external reference mode.
Note 5: Data valid to CLKOUT rise/fall timing is measured from 50% of data output level to 50% of clock output level.
Note 6: Guaranteed by design and characterization. Not subject to production testing.
Typical Operating Characteristics
(VAVDD = 1.8V, VOVDD = 1.8V, VCVDD = 1.8V, VGND = 0V, internal reference, differential input at -0.5dBFS, fIN = 5.3MHz, fCLK =
64MHz (50% duty cycle), DT = 0, CLOAD = 10pF, TA = +25°C, unless otherwise noted.)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
0
FFT PLOT
(16,384-POINT DATA RECORD)
MAX1438B toc01
fCLK = 64.0000006MHz
fIN = 5.3164063MHz
AIN = -0.5dBFS
SNR = 69.881dB
SINAD = 69.874dB
THD = -101.811dB
SFDR = 100.723dB
HD2 HD3
5 10 15 20 25 30
FREQUENCY (MHz)
FFT PLOT
(16,384-POINT DATA RECORD)
0 MAX1438B toc02
-10 fCLK = 64.0000001MHz
-20
fIN = 30.3007813MHz
AIN = -0.5dBFS
-30 SNR = 69.609dB
-40 SINAD = 69.585dB
THD = -92.323dBc
-50 SFDR = -92.870dBc
-60
-70
-80 HD2
-90
HD3
-100
-110
0
5 10 15 20 25 30
FREQUENCY (MHz)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
0
CROSSTALK
(16,384-POINT DATA RECORD)
MAX1438B toc03
MEASURED ON CHANNEL 1,
WITH INTERFERING SIGNAL
ON CHANNEL 2
fIN(N1) = 5.3164063MHz
fIN(N2) = 30.3007813MHz
CROSSTALK = -72.5dB
fIN(N2)
5 10 15 20 25 30
FREQUENCY (MHz)
_______________________________________________________________________________________ 5
5 Page 
www.DataSheet4U.com
Octal, 12-Bit, 64Msps, 1.8V ADC
with Serial LVDS Outputs
Pin Description (continued)
PIN NAME
FUNCTION
43 CLKOUTP Positive LVDS/SLVS Serial-Clock Output
45 OUT3N Channel 3 Negative LVDS/SLVS Output
46 OUT3P Channel 3 Positive LVDS/SLVS Output
47 OUT2N Channel 2 Negative LVDS/SLVS Output
48 OUT2P Channel 2 Positive LVDS/SLVS Output
50 OUT1N Channel 1 Negative LVDS/SLVS Output
51 OUT1P Channel 1 Positive LVDS/SLVS Output
53 OUT0N Channel 0 Negative LVDS/SLVS Output
54 OUT0P Channel 0 Positive LVDS/SLVS Output
LVDS Test Pattern Enable. Force LVDSTEST high to enable the output test pattern, 0000 1011 1101.
55 LVDSTEST As with the analog conversion results, the test pattern data are output LSB first. Force LVDSTEST
low for normal operation.
56
STBY
Standby Input. Force STBY high to put the MAX1438B into standby mode. In standby, the reference
circuitry remains active. Force STBY low for normal operation.
57
PLL3
PLL Control Input 3. See Table 1 for details.
58
PLL2
PLL Control Input 2. See Table 1 for details.
59
PLL1
PLL Control Input 1. See Table 1 for details.
Negative Reference Bypass Output. Connect a capacitor of at least 1µF (10µF typ) between REFP
61 REFN and REFN, and connect a capacitor of at least 1µF (10µF typ) between REFN and GND. Place the
capacitors as close as possible to the device on the same side of the PCB as the MAX1438B.
Positive Reference Bypass Output. Connect a capacitor of at least 1µF (10µF typ) between REFP
62 REFP and REFN, and connect a capacitor of at least 1µF (10µF typical) between REFN and GND. Place
the capacitors as close as possible to the device on the same side of the PCB as the MAX1438B.
Reference Input/Output. For internal reference operation (REFADJ = GND), the reference output
63 REFIO voltage is 1.24V. For external reference operation (REFADJ = AVDD), apply a stable reference
voltage at REFIO. Bypass to GND with a capacitor of at least 0.1µF.
Internal/External Reference Mode Select and Reference Adjust Input. For internal reference, connect
64 REFADJ REFADJ to GND. For external reference, connect REFADJ to AVDD. For adjusting the reference, see
the Full-Scale Range Adjustments Using the Internal Reference section.
65
CMOUT
Common-Mode Reference Voltage Output. CMOUT outputs the input common-mode voltage for
DC-coupled applications. Bypass CMOUT to GND with a capacitor of at least 0.1µF.
66
IN0P
Channel 0 Positive Input
67
IN0N
Channel 0 Negative Input
—
EP
Exposed Pad. Internally connected to GND. Connect EP to a large ground plane for maximum
thermal performance. Must be connected to GND.
______________________________________________________________________________________ 11
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| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet MAX1438B.PDF ] | |
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