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PDF ENC424J600 Data sheet ( Hoja de datos )

Número de pieza ENC424J600
Descripción (ENC424J600 / ENC624J600) Analog & Interface Products Ethernet
Fabricantes Microchip Technology 
Logotipo Microchip Technology Logotipo



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No Preview Available ! ENC424J600 Hoja de datos, Descripción, Manual

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ENC424J600/624J600
Data Sheet
Stand-Alone 10/100 Ethernet Controller
with SPI or Parallel Interface
© 2009 Microchip Technology Inc.
DS39935B

1 page




ENC424J600 pdf
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Pin Diagrams (Continued)
64-Pin TQFP
ENC424J600/624J600
CS/CS
SO/WR/WRL/EN/B0SEL
SI/RD/RW
SCK/AL/PSPCFG4
AD0
AD1
AD2
AD3
A0
A1
A2
A3
A4
VSS
VCAP
VDD
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
49
50
51
52
53
54
55
56 ENC624J600
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
VSSTX
TPOUT-
TPOUT+
VSSTX
VDDTX
TPIN-
TPIN+
VDDRX
VSSRX
VSSPLL
VDDPLL
VDD
A11
A10
PSPCFG3
PSPCFG2
© 2009 Microchip Technology Inc.
DS39935B-page 3

5 Page





ENC424J600 arduino
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2.0 EXTERNAL CONNECTIONS
2.1 Oscillator
ENC424J600/624J600 devices are designed to
operate from a fixed 25 MHz clock input. This clock can
be generated by an external CMOS clock oscillator or
a parallel resonant, fundamental mode 25 MHz crystal
attached to the OSC1 and OSC2 pins. Use of a crystal,
rated for series resonant operation, will oscillate at an
incorrect frequency. To comply with IEEE 802.3 Ethernet
timing requirements, the clock must have no more than
±50 ppm of total error; avoid using resonators or clock
generators that exceed this margin.
When clocking the device using a crystal, follow the
connections shown in Figure 2-1. When using a CMOS
clock oscillator or other external clock source, follow
Figure 2-2.
FIGURE 2-1:
CRYSTAL OSCILLATOR
OPERATION
C1(3)
OSC1
XTAL
RS(1)
C2(3)
OSC2
ENCX24J600
To Internal Logic
RF(2)
Note 1:
2:
3:
A series resistor, RS, may be required for
crystals with a low drive strength specification
or when using large loading capacitors.
The feedback resistor, RF , is typically 1.5 MΩ
(approx).
The load capacitors’ value should be derived
from the capacitive loading specification
provided by the crystal manufacture.
ENC424J600/624J600
FIGURE 2-2:
EXTERNAL CLOCK
SOURCE
3.3V Clock from
External System(1)
ENCX24J600
OSC1
Open
OSC2
Note 1: Duty cycle restrictions must be observed.
2.2 CLKOUT Pin
The Clock Out pin (CLKOUT) is provided for use as the
host controller clock or as a clock source for other
devices in the system. Its use is optional.
The 25 MHz clock applied to OSC1 is multiplied by a
PLL to internally generate a 100 MHz base clock. This
100 MHz clock is driven through a configurable
postscaler to yield a wide range of different CLKOUT
frequencies. The PLL multiplication adds clock jitter,
subject to the PLL jitter specification in Section 17.0
“Electrical Characteristics”. However, the postscaler
ensures that the clock will have a nearly ideal duty
cycle.
The CLKOUT function is enabled and the postscaler is
selected via the COCON<3:0> bits (ECON2<11:8>).
To create a clean clock signal, the CLKOUT output and
COCON bits are unaffected by all resets and
power-down modes. The CLKOUT function is enabled
out of POR and defaults to producing a 4 MHz clock.
This allows the device to directly clock the host
processor.
When the COCON bits are written with a new
configuration, the CLKOUT output transitions to the
new frequency without producing any glitches. No high
or low pulses with a shorter period than the original or
new clock are generated.
© 2009 Microchip Technology Inc.
DS39935B-page 9

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