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PDF ICS548A-03 Data sheet ( Hoja de datos )
| Número de pieza | ICS548A-03 | |
| Descripción | LOW SKEW CLOCK INVERTER AND DIVIDER | |
| Fabricantes | Integrated Device Technology | |
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LOW SKEW CLOCK INVERTER AND DIVIDER
DATASHEET
ICS548A-03
Description
The ICS548A-03 is a low cost, low skew, high-performance
general purpose clock designed to produce a set of one
output clock, one inverted output clock, and one clock
divided-by-two. Using our patented Phase-Locked Loop
(PLL) techniques, the device operates from a frequency
range of 10 MHz to 120 MHz in the PLL mode, and up to
160 MHz in the non-PLL mode.
In applications that need to maintain low phase noise in the
clock tree, the non-PLL (when S3=S2=1) modes should be
used.
This chip is not a zero delay buffer. Many applications may
be able to use the ICS527 for zero delay dividers.
Features
• Packaged in 16-pin SOIC (150 mil)
• Input clock up to 160 MHz in the non-PLL mode
• Provides clock outputs of CLK, CLK, and CLK/2
• Low skew (500 ps) on CLK, CLK, and CLK/2
• All outputs can be tri-stated
• Entire chip can be powered down by changing one or two
select pins
• 3.3 V operating range
• Available in commercial and industrial temperature
ranges
• RoHS 5 (green) or RoHS 6 (green and lead free)
compliant package
Block Diagram
S3:S0
4
Clock
input
Input
Buffer
VDD
2
GND
2
Clock
Synthesis
and Divider
Circuitry
CLK
CLK
CLK/2
OE (all outputs)
IDT™ / ICS™ LOW SKEW CLOCK INVERTER AND DIVIDER
1
ICS548A-03 REV C 063006
1 page  
ICS548A-03
LOW SKEW CLOCK INVERTER AND DIVIDER
www.DataSheet4U.com
CLOCK DIVIDER
AC Electrical Characteristics
VDD = 3.3 V, Ambient Temperature -40 to +85°C, unless stated otherwise
Parameter
Symbol
Conditions
Min. Typ. Max. Units
Input Frequency, clock
input, PLL on
fIN
10 120 MHz
Input Frequency, clock
input, PLL off
fIN
0 160 MHz
Output Frequency (see
table on page 2)
fOUT Mode dependent
0 120 MHz
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle
Output Enable Time, OE
high to output on
tOR 0.8 to 2.0 V
tOF 2.0 to 0.8 V
tDC At VDD/2
0.84 ns
0.74 ns
45 50 55 %
50 ns
Output Disable Time, OE
to tri-state
50 ns
Absolute Clock Period
Jitter. PLL modes
Deviation from mean
150 ps
One Sigma Clock Period
Jitter, PLL modes
60 ps
Output clock skew for
CLK, CLK, or CLK/2
At VDD/2
850 ps
Note 1: The phase relationship between input and output clocks can change at power up. Use the ICS570 or
ICS527 Zero Delay Buffers for a guaranteed phase relationship.
Thermal Characteristics
Parameter
Symbol Conditions
Thermal Resistance Junction to
Ambient
θJA Still air
θJA 1 m/s air flow
θJA 3 m/s air flow
Thermal Resistance Junction to Case θJC
Min.
Typ.
120
115
105
58
Max.
Units
°C/W
°C/W
°C/W
°C/W
IDT™ / ICS™ LOW SKEW CLOCK INVERTER AND DIVIDER
5
ICS548A-03 REV C 063006
5 Page | ||
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