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PDF AD5732 Data sheet ( Hoja de datos )
| Número de pieza | AD5732 | |
| Descripción | (AD57x2) Voltage Output DACs | |
| Fabricantes | Analog Devices | |
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Complete, Dual, 12-/14-/16-Bit, Serial
Input, Unipolar/Bipolar, Voltage Output DACs
AD5722/AD5732/AD5752
FEATURES
Complete, dual, 12-/14-/16-bit digital-to-analog converter (DAC)
Operates from single/dual supplies
Software programmable output range
+5 V, +10 V, +10.8 V, ±5 V, ±10 V, ±10.8 V
INL error: ±16 LSB maximum, DNL error: ±1 LSB maximum
Total unadjusted error (TUE): 0.1% FSR maximum
Settling time: 10 µs typical
Integrated reference buffers
Output control during power-up/brownout
Simultaneous updating via LDAC
Asynchronous CLR to zero scale or midscale
DSP-/microcontroller-compatible serial interface
24-lead TSSOP
Operating temperature range: −40°C to +85°C
iCMOS process technology1
APPLICATIONS
Industrial automation
Closed-loop servo control, process control
Automotive test and measurement
Programmable logic controllers
GENERAL DESCRIPTION
The AD5722/AD5732/AD5752 are dual, 12-/14-/16-bit, serial
input, voltage output, digital-to-analog converters. They operate
from single-supply voltages from +4.5 V up to +16.5 V or dual-
supply voltages from ±4.5 V up to ±16.5 V. Nominal full-scale
output range is software-selectable from +5 V, +10 V, +10.8 V,
±5 V, ±10 V, or ±10.8 V. Integrated output amplifiers, reference
buffers, and proprietary power-up/power-down control circuitry
are also provided.
The parts offer guaranteed monotonicity, integral nonlinearity
(INL) of ±16 LSB maximum, low noise, and 10 µs typical
settling time.
The AD5722/AD5732/AD5752 use a serial interface that
operates at clock rates up to 30 MHz and are compatible with
DSP and microcontroller interface standards. Double buffering
allows the simultaneous updating of all DACs. The input coding
is user-selectable twos complement or offset binary for a bipolar
output (depending on the state of Pin BIN/2sComp), and
straight binary for a unipolar output. The asynchronous clear
function clears all DAC registers to a user-selectable zero-scale
or midscale output. The parts are available in a 24-lead TSSOP
and offer guaranteed specifications over the −40°C to +85°C
industrial temperature range.
The AD5722/AD5732/AD5752 are pin compatible with the
AD5724/AD5734/AD5754, which are complete, quad, 12-/14-/
16-bit, serial input, unipolar/bipolar voltage output DACs.
FUNCTIONAL BLOCK DIAGRAM
AVSS AVDD
REFIN
DVCC
CLR
BIN/2sCOMP
SDIN
SCLK
SYNC
SDO
AD5722/AD5732/AD5752
REFERENCE
BUFFERS
INPUT SHIFT
REGISTER
AND
CONTROL
LOGIC
12/14/16
INPUT
REGISTER A
DAC
12/14/16
REGISTER A
DAC A
INPUT
REGISTER B
DAC
12/14/16
REGISTER B
DAC B
VOUTA
VOUTB
GND
LDAC
Figure 1.
DAC_GND (2) SIG_GND (2)
1 For analog systems designers within industrial/instrumentation equipment OEMs who need high performance ICs at higher voltage levels, iCMOS® is a technology
platform that enables the development of analog ICs capable of 30 V and operating at ±15 V supplies while allowing dramatic reductions in power consumption and
package size, as well as increased ac and dc performance.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.
1 page  
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AD5722/AD5732/AD5752
AC PERFORMANCE CHARACTERISTICS
AVDD = 4.5 V1 to 16.5 V; AVSS = −4.5 V to −16.5 V, or AVSS = 0 V; GND = 0 V; REFIN = 2.5 V; DVCC = 2.7 V to 5.5 V; RLOAD = 2 kΩ;
CLOAD = 200 pF; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter2
DYNAMIC PERFORMANCE
Output Voltage Settling Time
Slew Rate
Digital-to-Analog Glitch Energy
Glitch Impulse Peak Amplitude
Digital Crosstalk
DAC-to-DAC Crosstalk
Digital Feedthrough
Output Noise
0.1 Hz to 10 Hz Bandwidth
100 kHz Bandwidth
Output Noise Spectral Density
Min Typ Max Unit
Test Conditions/Comments
10 12
7.5 8.5
5
3.5
13
35
10
10
0.6
μs
μs
μs
V/μs
nV-sec
mV
nV-sec
nV-sec
nV-sec
20 V step to ±0.03% FSR
10 V step to ±0.03% FSR
512 LSB step settling (16-bit resolution)
15 μV p-p 0x8000 DAC code
80 μV rms
320 nV/√Hz Measured at 10 kHz, 0x8000 DAC code
1 For specified performance, the maximum headroom requirement is 0.9 V.
2 Guaranteed by design and characterization; not production tested.
TIMING CHARACTERISTICS
AVDD = 4.5 V to 16.5 V; AVSS = −4.5 V to −16.5 V, or AVSS = 0 V; GND = 0 V; REFIN = 2.5 V; DVCC = 2.7 V to 5.5 V; RLOAD = 2 kΩ; CLOAD =
200 pF; all specifications tMIN to tMAX, unless otherwise noted.
Table 3.
Parameter1, 2, 3
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t154
t164
t17
Limit at tMIN, tMAX
33
13
13
13
13
100
5
0
20
20
20
10
20
2.5
13
40
200
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
μs max
ns min
μs max
ns min
ns max
ns min
Description
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time (write mode)
Data setup time
Data hold time
LDAC falling edge to SYNC falling edge
SYNC rising edge to LDAC falling edge
LDAC pulse width low
DAC output settling time
CLR pulse width low
CLR pulse activation time
SYNC rising edge to SCLK falling edge
SCLK rising edge to SDO valid (CL SDO5 = 15 pF)
Minimum SYNC high time (readback/daisy-chain mode)
1 Guaranteed by characterization; not production tested.
2 All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.
3 See Figure 2, Figure 3, and Figure 4.
4 Daisy-chain and readback mode.
5 CL SDO = capacitive load on SDO output.
Rev. 0 | Page 5 of 32
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8
6
4
MAX INL ±10V
2 MAX INL ±5V
MIN INL ±10V
MIN INL ±5V
0 MAX INL +10V
MIN INL +10V
MAX INL +5V
–2 MIN INL +5V
–4
–6
–8
–40
–20
0
20 40 60 80
TEMPERATURE (°C)
Figure 12. AD5752 Integral Nonlinearity Error vs. Temperature
0.1
0
–0.1 MAX DNL ±10V
MAX DNL ±5V
MIN DNL ±10V
–0.2 MIN DNL ±5V
MAX DNL +10V
MIN DNL +10V
MAX DNL +5V
–0.3 MIN DNL +5V
–0.4
–0.5
–0.6
–40
–20
0
20 40 60 80
TEMPERATURE (°C)
Figure 13. AD5752 Differential Nonlinearity Error vs. Temperature
10
8
6
4
2
BIPOLAR 10V MIN
0
UNIPOLAR 10V MIN
BIPOLAR 10V MAX
UNIPOLAR 10V MAX
–2
–4
–6
–8
–10
11.5 12.0 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5
SUPPLY VOLTAGE (V)
Figure 14. AD5752 Integral Nonlinearity Error vs. Supply Voltage
AD5722/AD5732/AD5752
10
8
6
4
2
BIPOLAR 5V MIN
0
UNIPOLAR 5V MIN
BIPOLAR 5V MAX
UNIPOLAR 5V MAX
–2
–4
–6
–8
–10
5.5 6.5 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5
SUPPLY VOLTAGE (V)
Figure 15. AD5752 Integral Nonlinearity Error vs. Supply Voltage
1.0
BIPOLAR 10V MIN
0.8
UNIPOLAR 10V MIN
BIPOLAR 10V MAX
UNIPOLAR 10V MAX
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
11.5 12.0 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5
SUPPLY VOLTAGE (V)
Figure 16. AD5752 Differential Nonlinearity Error vs. Supply Voltage
1.0
BIPOLAR 5V MIN
0.8
UNIPOLAR 5V MIN
BIPOLAR 5V MAX
UNIPOLAR 5V MAX
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
5.5 6.5 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5
SUPPLY VOLTAGE (V)
Figure 17. AD5752 Differential Nonlinearity Error vs. Supply Voltage
Rev. 0 | Page 11 of 32
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD5732.PDF ] | |
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