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PDF LF48410JC25 Data sheet ( Hoja de datos )
| Número de pieza | LF48410JC25 | |
| Descripción | 1024 x 24-bit Video Histogrammer | |
| Fabricantes | LOGIC Devices Incorporated | |
| Logotipo |  |
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DEVICES INCORPORATED
DEVICES INCORPORATED
LF48410
1024 x 24-bit VideoLHFis4to8gr4am1m0er
1024 x 24-bit Video Histogrammer
FEATURES
DESCRIPTION
u 40 MHz Data Input and Compu-
tation Rate
u 1024 x 24-bit Memory Array
u Histograms of Images up to 4K x
4K with 10-bit Pixel Resolution
u Memory Array Flash Clear
u User-Programmable Modes:
Histogram, Histogram Accumulate,
Look Up Table, Bin Accumulate,
Delay Memory, Delay and Subtract,
Single Port RAM
u Replaces Harris HSP48410
u 84-pin PLCC, J-Lead
The LF48410 is capable of generating
histograms and Cumulative Distribu-
tion Functions of video images. It
may also be used as a look up table, a
bin accumulator, a delay memory
(delay and subtract also possible), or a
single port RAM. The on-chip 1024 x
24-bit memory array facilitates
histograms of images up to 4K x 4K
pixels with a 10-bit pixel resolution.
Once the histogram of a video image
is stored in the memory array, the
Cumulative Distribution Function can
be calculated by putting the device in
Histogram Accumulate Mode.
Transformation functions can be
performed on pixel values when the
device is in Look Up Table Mode. If
the Cumulative Distribution Function
is the desired transformation func-
tion, the LF48410 can calculate it and
have it available for Look Up Table
Mode. When the device is in Delay
Memory Mode, it functions as a video
row buffer. In this mode, the LF48410
can buffer video lines as long as 1029
pixels. The device can also function
as an asynchronous single port RAM.
During asynchronous modes, the
device can be configured as a 1024 x
24, 1024 x 16, or 1024 x 8-bit RAM. A
Flash Clear function is provided
which sets all memory array locations
and data path registers to “0”.
LF48410 BLOCK DIAGRAM
24
DIN23-0
IOA9-0
PIN9-0
10
10
CLK
(TO ALL REGISTERS)
WR
RD
UWS
START
FC
FCT2-0
LD
3
RAM ARRAY
DATA IN
DATA OUT
ADDRESS WR
ADDRESS
GENERATOR
COUNTER
ADDER
INPUT
CONTROL
CONTROL
FUNCTION
DECODE
MUX CONTROL SIGNALS
1
24
DIO DIO23-0
I/F
Video Imaging Products
08/08/2000–LDS.48410-L
1 page  
DEVICES INCORPORATED
LF48410
1024 x 24-bit Video Histogrammer
example, to set the number of delays
to 10, START would have to be set
LOW every 6 cycles. The maximum
delay length is 1029 and the minimum
delay length is 6. Data on DIN23-0
is latched on the rising edge of
CLK and loaded into the memory
array at the address defined by the
counter. Data is output on DIO23-0 (if
RD is LOW). If the counter reaches
the value of 1023, the counter will
hold this value and writing to the
memory array will be disabled.
FIGURE 5. DELAY MEMORY MODE
24
DIN23-0
CLK
(TO ALL REGISTERS)
START
RAM ARRAY
DATA IN
DATA OUT
ADDRESS WR
COUNTER
CONTROL
"0"
24
DIO
I/F
DIO23-0
RD
DELAY AND SUBTRACT MODE
NOTE: NUMBER IN REGISTER INDICATES
NUMBER OF PIPELINE DELAYS.
When the LF48410 is in this mode, the
chip is configured as shown in Figure 6.
The internal counter is used to gener-
ate address data for the memory
array. When START goes LOW, the
counter is reset to zero. Delay length
(row length) is determined by
reseting the counter every N–4 clock
cycles, where N is the number of
delays. The maximum delay length is
1029 and the minimum delay length
is 6. Data on DIN23-0 is latched on the
rising edge of CLK and loaded into
the memory array at the address
defined by the counter. Data is
output on DIO23-0 (if RD is LOW).
Before data read from the memory
array is output to DIO23-0, input data
is subtracted from it according to the
following formula: OUTC = D(C–N+1) –
D(C–3). OUTC is the data sent to the
output port (DIO23-0) on clock cycle C.
D(C–N+1) is the data latched into the
device on clock cycle C–N+1, and D(C-
3) is the data latched into the device on
clock cycle C–3. N is the number of
delays. For example, to determine
what will be output on DIO23-0 on
clock cycle 12 when the device is set
for 10 delays, set C=12 and N=10 to
obtain: OUT12 = D3 – D9. If the
counter reaches the value of 1023, the
counter will hold this value and
writing to the memory array will be
disabled.
FIGURE 6. DELAY AND SUBTRACT MODE
24
DIN23-0
CLK
(TO ALL REGISTERS)
START
RAM ARRAY
DATA IN
DATA OUT
ADDRESS WR
COUNTER
–DIN23-0
CONTROL
24
DIO
I/F
DIO23-0
RD
NOTE: NUMBER IN REGISTER INDICATES
NUMBER OF PIPELINE DELAYS.
ASYNCHRONOUS 16 MODE
When the LF48410 is in this mode, the
chip is configured as shown in Figure 7.
This mode allows the device to
function as an asynchronous single
port RAM. Each 24-bit memory
location is split into two parts, the
lower 16 bits and the upper 8 bits.
IOA9-0 addresses the 24-bit memory
locations, and UWS addresses the
lower 16 or upper 8 bits of those
locations. If UWS is LOW, the lower
16 bits of the 24-bit memory location
are addressed. If UWS is HIGH, the
upper 8 bits are addressed. Address
data on IOA9-0 and UWS is latched
into the device on the falling edge of
RD or WR. If RD latches the address
data, a memory read is performed.
Data at the specified address is
output on DIO15-0 (if UWS was
latched LOW) or DIO7-0 (if UWS was
latched HIGH). If UWS was latched
LOW/HIGH, DIO16-23/DIO8-23 will
output zeros during a memory read.
If WR latches the address data, a
memory write is performed. After
the falling edge of WR latches the
address, data on DIO15-0 (if UWS was
latched LOW) or DIO7-0 (if UWS was
latched HIGH) is written to the RAM
on the rising edge of WR.
Video Imaging Products
5 08/08/2000–LDS.48410-L
5 Page 
DEVICES INCORPORATED
LF48410
1024 x 24-bit Video Histogrammer
SWITCHING WAVEFORMS: LOOK UP TABLE WRITE MODE
CLK
START*
DIN23-0
RD
DIO23-0
123
tSS
tDH
tDS
1
2
3
tD
tDIS
tENA
HIGH IMPEDANCE
45
tPWH
tPWL
tCYC
45
6
6
123
7
7
4
*START must be held LOW a minimum of tSH after the rising edge of CLK that loads the last value of DIN23-0.
SWITCHING WAVEFORMS: LOOK UP TABLE READ MODE
CLK
START*
PIN9-0
RD
DIO23-0
1
tSS
234
tPWH
tPWL
tDH
tDS
1
2
5
tCYC
3
tDIS
tENA
HIGH IMPEDANCE
6
4
tD
*START must be held HIGH a minimum of tSH after the rising edge of CLK that loads the last value of PIN9-0.
7
5
1
SWITCHING WAVEFORMS: DELAY MEMORY/DELAY AND SUBTRACT MODE
CLK
START
DIN23-0
1 2 3 4 5 6 7 8 9 10 11 12 13 14
tSH
tSS
tPWL
tPWH
tSH
tSS
tCYC
tSH
tSS
tDH
tDS
tSH
tSS
1 2 3 4 5 6 7 8 9 10
tSH
tSS
11 12 13
14
RD
DIO23-0
tDIS
tENA
HIGH IMPEDANCE
Shown are the waveforms for a delay length of 10.
tD
1234
Video Imaging Products
11 08/08/2000–LDS.48410-L
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet LF48410JC25.PDF ] | |
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