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PDF VE890 Data sheet ( Hoja de datos )
| Número de pieza | VE890 | |
| Descripción | Voice Solution | |
| Fabricantes | Zarlink | |
| Logotipo |  |
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www.DataSheet4U.com
A Voice Solution
FEATURES
Complete 1FXS chipset for VoIP
access devices
Implements all the key BORSHT
functions
Built-in DC/DC controller
configurable for buck-boost or
flyback operation
Integrated balanced ringing
generator capable of driving
5 REN at 70 VPK or 3 REN at
92 VPK
Low Power Standby with 50 mW
typical On-Hook dissipation
Standard 8 kHz and Wideband
16 kHz sample rates
Single hardware design with
software support for worldwide
markets
VoicePathTM API-II Software
— Significantly reduces
development and testing time
— Enables modular designs based
on the VE8910 and other
members of the VE890 Series for
1FXS, 1FXS+1FXO, and
2FXS+1FXO product variants
— Allows for a seamless migration
between products using a
common software architecture
— Supported by SDK, development
board, and reference designs
Support for GR-909/TIA-1063
metallic loop (line) testing using
VeriVoiceTM Test Suite software
APPLICATIONS
Residential and SOHO VoIP CPE, such as ADSL2+/VDSL2 Integrated Access
Devices (IADs), Analog Telephone Adapters (ATAs), and VoIP Gateways
™
VE890 Series
VE8910 Chipset
1FXS
PACKAGE OPTIONS
48-Pin LQFP
1(6w-iPdein) SOIC
PIN ASSIGNMENTS
LFC
SWIS
SWISG
SWVS
SWCMP
SWOUT
SWOUT
DVDD
I/O1
DGND
I/O2
RST
48 47 46 45 44 43 42 41 40 39 38 37
1 36
2 35
3 34
4 33
5 32
6 Le89116 SLAC
7 LQFP-48
31
30
8 29
9 28
10 27
11 26
12 25
13 14 15 16 17 18 19 20 21 22 23 24
IBO
TFLT
IBT
IBR
RSVD
AGND
RSVD
AVDD
RSVD
CSMODE
I/O3
I/O4
DESCRIPTION
The VE8910 chipset is an integrated, low-cost 1FXS chipset that is optimized for VoIP
access devices. The chipset implements a complete BORSHT functionality by
providing the necessary voice interface functions to power, ring, signal, and connect
one or more telephones. On the digital side, the VE8910 chipset provides standard MPI
and PCM interfaces to leading VoIP processors. The VE8910 features low power
consumption in all modes of operation; In on-hook Low Power Standby, it typically
draws 50 mW, less than half that of its nearest competitor.
The VE8910 chipset is supported by the Zarlink VoicePath™ API-II (VP API-II) software
package, which enables designers to program a single hardware circuit for worldwide
markets. The VP API-II 'C' code is used to abstract the Zarlink devices from application
code while providing functions for controlling, supervising, and testing a set of
subscriber lines. The Zarlink VeriVoice™ Test Suite software package provides metallic
loop testing based on the Telcordia GR-909 and TIA-1063 recommendations.
FUNCTIONAL BLOCK DIAGRAM
TIP 1
VBAT 2
BGND 3
VCC 4
RSN 5
LSN 6
VREF 7
IBI 8
Le89810 SLIC
SOIC-16 (Wide)
16 RING
15 RSVD
14 RSVD
13 AGND
12 RSVD
11 IBR
10 IBT
9 TFLT
Telephone
FXS
Le89810 SLIC
Tip &
Ring
Line
Driver
Level
Shifting
Buffer
Le89116 SLAC
Line Driver
Interface
S w itch in g
Regulator
Controller
Audio
Processing
Analog Ref.
& PLL
Supervision,
Control, &
Test
µProcessor
Interface
(M P I)
PCM Interface
& Time Slot
Assigner
(TSA)
VoIP Processor
VoicePath
API-II
Software
NOTE: On August 3, 2007, Zarlink Semiconductor acquired the products and Document ID# 081575 Date: February 4, 2009
technology of Legerity Holdings.
Distribution: Protected
1 page  
VE8910
Data Sheet
2.2.2
Features Overview
www.DataSheet4U.com
The features directly supported by VP API-II are dependent upon the underlying SLAC device’s capabilities. For the VE8910
chipset, the following features are supported:
• AC and DC Coefficient Programming
• Ringing Parameter (amplitude, frequency, bias, type)
• Tone Generation (frequency and amplitude)
• Highly Programmable Tone and Ringing Cadence
• Caller ID Generation (Types I and II)
• Loop Start Signaling, including Dial Pulse Detection
• Seamless integration of the Zarlink VeriVoice Test Packages for GR-909 Metallic Loop Testing
• Four modes of interrupt support
2.2.3
Configuring VP API-II for the VE8910 Chipset
Two main functions in VP API-II are required in all applications:
1. VpMakeDeviceObject() - Configures a specific device (chip select) to a device context. Provides VP API-II with device spe-
cific type (deviceType).
2. VpMakeLineObject() - Configures a specific line (channel) to a line and device context. Provides VP API-II with line specific
type (termType).
When using the VE8910 chipset, the following settings must be used:
• The value for deviceType in VpMakeDeviceObject() must be: VP_DEV_890_SERIES
• The value for termType in VpMakeLineObject() must be
– VP_TERM_FXS_GENERIC when channelId = 0 and Normal Standby operation is desired
– VP_TERM_FXS_LOW_PWR when channelId = 0 and Low Power Standby operation is desired. Note that this feature
requires that the resistor RLP shown on SLIC and SLAC Application Circuit, on page 49 be populated.
Please refer to VoicePath API-II CSLAC Reference Guide for additional details.
2.3 VoicePath Profile Wizard
The VP Profile Wizard is a Windows-based application that lets the user select the values of all the Profiles that are supported
by the VP API-II. It automatically generates the coefficient files that the API needs to operate. Figure 3 shows a typical screenshot
for getting started and creating a new project for the VE8910 chipset and other members of the VE890 Series.
5
Zarlink Semiconductor Inc.
5 Page 
VE8910
Data Sheet
• Permits adjustment of the two-wire termination impedance
www.Da• taShPereotv4iUd.ecsomfrequency attenuation adjustment (equalization) of the receive and transmit paths
All programmable digital filter coefficients can be calculated using the Zarlink WinSLAC™ software. The PCM codes can be either
16-bit linear two's-complement or 8-bit companded A-law or µ-law.
Besides the codec functions, the integrated voice processing block provides all the sensing, feedback, and clocking necessary
to completely control SLIC device functions with programmable parameters. System-level parameters under programmable
control include active loop current limits, open circuit feed voltages, and loop supervision thresholds.
The Le89116 SLAC device is architected in such a way as to reduce the real time demands on the host processor. An integrated
cadencer/sequencer controls ringing and call progress tone generation. This feature can also generate timed interrupts and
substantially reduces the user’s need to implement time critical functions.
For subscriber line diagnostics, AC and DC line conditions can be monitored by connecting analog currents and voltages to the
voice A/D converter. This gives the system’s host processor the ability to configure the system and make system and line tests.
Both longitudinal and metallic resistance and capacitance can be measured. This allows identification of leakage resistance, line
capacitance, and the presence and status of telephones. These tests are all supported by the Zarlink VeriVoice software.
PTCA
TIP
RING
Figure 6. Voice Signal Processing Block Diagram
High Voltage
LineDriver
+
AR* DAC
+ DRL* +
Inter-
polator
+
Inter-
polator
Signal Generators
A, B, CandD
(Ringing, FSK,
Call Progress)
1kHz
Tone
(TON)
0
GR* R* LPF + RI*
(C/L)
Expander
(CRP)
(TON)
From
PCM
Block
IRSN
RTV
RTV
TAC
V to I
Converter
RTAC CTAC Transmit
RAC Buffer
ADC Deci-
&AX mator
(LRG) Lower
Receive Gain
Linear Mode
DISN* Z* B*
* Programmable Blocks
High
Pass
Filter
Deci-
mator
+
GX*
X*
NF &
HPF
LPF
Com- (C/L)
pressor
To
PCM
(ILB) Block
RRAC CRAC
(HPF)
High Pass Filter
Linear Mode
3.3.1.2 Impedance Synthesis
The analog impedance synthesis loop is comprised of the SLIC, the AC sense path components, the transmit amplifier, and a
voltage to current converter. An external resistor, RTV, synthesizes the nominal impedance in the analog domain. Additional
refinement of the impedance is done in the DSP via the Digital Impedance Scaling Network (DISN) and Z-blocks.
The DISN path is comprised of the voice A/D and its first stage of decimation, a DISN, and the voice DAC. The 8-bit DISN
synthesizes a portion of the AC impedance which appears in parallel with RTV and is used to modify the impedance set by the
external analog network.
The Z Filter is a programmable digital filter providing an additional path and programming flexibility over the DISN in modifying
the transfer function of the synthesis loop. Together RTV , DISN, and the Z Filter enable the user to synthesize virtually all required
telephony device input impedances.
3.3.1.3 Frequency Response Correction and Equalization
The voice signal processor contains programmable filters in the receive (R) and transmit (X) directions that may be programmed
for line equalization and to correct any attenuation distortion caused by the Z Filter.
3.3.1.4 Transhybrid Balancing
The voice signal processor’s programmable B Filter is used to adjust transhybrid balance. The filter has a single pole Infinite
Impulse Response (IIR) section and an eight-tap Finite Impulse Response (FIR) section, both operating at 16 kHz.
11
Zarlink Semiconductor Inc.
11 Page | ||
| Páginas | Total 60 Páginas | |
| PDF Descargar | [ Datasheet VE890.PDF ] | |
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