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ICS - 64-Pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor

Numéro de référence ICS9LPRS365
Description 64-Pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor
Fabricant ICS 
Logo ICS 





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ICS9LPRS365 fiche technique
Integrated
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ICS9LPRS365
Advance Information
64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor
Recommended Application:
Pin Configuration
CK505 compliant clock with fully integrated voltage regulator
and Internal series resistor on differential outputs
Pin
Define
PCI0/CR#_A 1
VDDPCI 2
PCI1/CR#_B 3
64 SCLK
63 SDATA
62 REF0/FSLC/TEST_SEL
PCI2/TME 4
61 VDDREF
Output Features:
PCI3 5
60 X1
• 2 - CPU differential low power push-pull pairs
• 9 - SRC differential low power push-pull pairs
PCI4/27_Select 6
PCI_F5/ITP_EN 7
GNDPCI 8
59 X2
58 GNDREF
57 FSLB/TEST_MODE
• 1 - CPU/SRC selectable differential low power push-pull
pair
VDD48 9
USB_48MHz/FSLA 10
56 CK_PWRGD/PD#
55 VDDCPU
• 1 - SRC/DOT selectable differential low power push-pull
pair
GND48 11
VDD96_IO 12
SRCT0/DOTT_96 13
Top
View
54 CPUT0
53 CPUC0
52 GNDCPU
• 5 - PCI, 33MHz
SRCC0/DOTC_96 14
51 CPUT1_F
• 1 - PCI_F, 33MHz free running
• 1 - USB, 48MHz
GND 15
VDDPLL3 16
27MHz_NonSS/SRCT1/SE1 17
50 CPUC1_F
49 VDDCPU_IO
48 NC
• 1 - REF, 14.318MHz
27MHz_SS/SRCC1/SE2 18
47 CPUT2_ITP/SRCT8
GND 19
46 CPUC2_ITP/SRCC8
VDDPLL3_IO 20
45 VDDSRC_IO
Key Specifications:
SRCT2/SATAT 21
44 SRCT7/CR#_F
• CPU outputs cycle-cycle jitter < 85ps
• SRC output cycle-cycle jitter < 125ps
SRCC2/SATAC 22
GNDSRC 23
SRCT3/CR#_C 24
43 SRCC7/CR#_E
42 GNDSRC
41 SRCT6
• PCI outputs cycle-cycle jitter < 250ps
SRCC3/CR#_D 25
40 SRCC6
• +/- 100ppm frequency accuracy on CPU & SRC clocks
VDDSRC_IO 26
SRCT4 27
39 VDDSRC
38 PCI_STOP#
SRCC4 28
37 CPU_STOP#
Features/Benefits:
• Does not require external pass transistor for voltage
regulator
GNDSRC 29
SRCT9 30
SRCC9 31
SRCC11/CR#_G 32
36 VDDSRC_IO
35 SRCC10
34 SRCT10
33 SRCT11/CR#_H
• Integrated series resistors on differential outputs, Zo=50
64-TSSOP
• Supports spread spectrum modulation, default is 0.5%
down spread
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
• Uses external 14.318MHz crystal, external crystal load
caps are required for frequency tuning
• Selectable between one SRC differential push-pull pair
and two single-ended outputs
Table 1: CPU Frequency Select Table
FSLC2
B0b7
FSLB1
B0b6
FSLA1
B0b5
CPU
MHz
SRC
MHz
PCI
MHz
REF
MHz
USB
MHz
00
0 266.66
00
1 133.33
01
01
0 200.00
1 166.66 100.00 33.33 14.318 48.00
10
0 333.33
10
1 100.00
11
11
0 400.00
1
Reserved
1. FSLA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2. FSLC is a three-level input. Please see the VIL_FS and VIH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
1218—07/11/06
DOT
MHz
96.00
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.

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