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PDF KK4023B Data sheet ( Hoja de datos )
| Número de pieza | KK4023B | |
| Descripción | Triple 3-Input NAND Gate High-Voltage Silicon-Gate CMOS | |
| Fabricantes | KODENSHI KOREA | |
| Logotipo |  |
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Triple 3-Input NAND Gate
High-Voltage Silicon-Gate CMOS
TECHNICAL DATA
KK4023B
The KK4023B NAND gates provide the system designer with direct
emplementation of the NAND function.
• Operating Voltage Range: 3.0 to 18 V
• Maximum input current of 1 µA at 18 V over full package-temperature
range; 100 nA at 18 V and 25°C
• Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
ORDERING INFORMATION
KK4023BN Plastic
KK4023BD SOIC
TA = -55° to 125° C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
PIN 14 =VCC
PIN 7 = GND
FUNCTION TABLE
Inputs
AB
LX
XL
XX
HH
X = don’t care
C
X
X
L
H
Output
Y
H
H
H
L
1
1 page  
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KK4023B
N SUFFIX PLASTIC DIP
(MS - 001AA)
A
14 8
B
17
FL
C
-T- SEATING
PLANE
N
G KM
D
0.25 (0.010) M T
J
H
NOTES:
1. Dimensions “A”, “B” do not include mold flash or protrusions. Maximum
mold flash or protrusions 0.25 mm (0.010) per side.
Symbol
A
B
C
D
F
G
H
J
K
L
M
N
Dimensions, mm
MIN MAX
18.67 19.69
6.10 7.11
5.33
0.36 0.56
1.14 1.78
2.54
7.62
0° 10°
2.92 3.81
7.62 8.26
0.20 0.36
0.38
D SUFFIX SOIC
(MS - 012AB)
A
14 8
H BP
1G
7
C
R x 45
-T-
D
SEATING
K PLANE
J
F
M
0.25 (0.010) M T C M
NOTES:
1.Dimensions A and B do not include mold flash or protrusion.
2.Maximum mold flash or protrusion 0.15 mm (0.006) per side for A; for
B - 0.25 mm (0.010) per side.
Dimensions, mm
Symbol. MIN MAX
A 8.55 8.75
B 3.80 4.00
C 1.35 1.75
D 0.33 0.51
F 0.40 1.27
G 1.27
H 5.72
J 0° 8°
K 0.10 0.25
M 0.19 0.25
P 5.80 6.20
R 0.25 0.50
5
5 Page | ||
| Páginas | Total 5 Páginas | |
| PDF Descargar | [ Datasheet KK4023B.PDF ] | |
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