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PDF TJA1042 Data sheet ( Hoja de datos )
| Número de pieza | TJA1042 | |
| Descripción | High-speed CAN Transceiver | |
| Fabricantes | NXP Semiconductors | |
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TJA1042
High-speed CAN transceiver with Standby mode
Rev. 8 — 15 January 2015
Product data sheet
1. General description
The TJA1042 high-speed CAN transceiver provides an interface between a Controller
Area Network (CAN) protocol controller and the physical two-wire CAN bus. The
transceiver is designed for high-speed CAN applications in the automotive industry,
providing the differential transmit and receive capability to (a microcontroller with) a CAN
protocol controller.
The TJA1042 belongs to the third generation of high-speed CAN transceivers from NXP
Semiconductors, offering significant improvements over first- and second-generation
devices such as the TJA1040. It offers improved ElectroMagnetic Compatibility (EMC)
and ElectroStatic Discharge (ESD) performance, and also features:
• Ideal passive behavior to the CAN bus when the supply voltage is off
• A very low-current Standby mode with bus wake-up capability
• TJA1042T/3 and TJA1042TK/3 can be interfaced directly to microcontrollers with
supply voltages from 3 V to 5 V
The TJA1042 implements the CAN physical layer as defined in the current ISO11898
standard (ISO11898-2:2003, ISO11898-5:2007). Pending the release of the updated
version of ISO11898-2 including CAN FD, additional timing parameters defining loop
delay symmetry are specified. This implementation enables reliable communication in the
CAN FD fast phase at data rates up to 2 Mbit/s.
These features make the TJA1042 an excellent choice for all types of HS-CAN networks,
in nodes that require a low-power mode with wake-up capability via the CAN bus.
2. Features and benefits
2.1 General
Fully ISO 11898-2:2003 and ISO 11898-5:2007 compliant
Loop delay symmetry timing enables reliable communication at data rates up to
2 Mbit/s in the CAN FD fast phase
Suitable for 12 V and 24 V systems
Low ElectroMagnetic Emission (EME) and high ElectroMagnetic Immunity (EMI)
VIO input on TJA1042T/3 and TJA1042TK/3 allows for direct interfacing with 3 V to 5 V
microcontrollers
SPLIT voltage output on TJA1042T for stabilizing the recessive bus level
Available in SO8 package and leadless HVSON8 package (3.0 mm 3.0 mm) with
improved Automated Optical Inspection (AOI) capability
1 page  
NXP Semiconductors
TJA1042
High-speed CAN transceiver with Standby mode
7. Functional description
The TJA1042 is a HS-CAN stand-alone transceiver with Standby mode. It combines the
functionality of the PCA82C250, PCA82C251 and TJA1040 transceivers with improved
EMC and ESD handling capability and quiescent current performance. Improved slope
control and high DC handling capability on the bus pins provide additional application
flexibility.
The TJA1042 is available in two versions, distinguished only by the function of pin 5:
• The TJA1042T is backwards compatible with the TJA1040 when used with a 5 V
microcontroller, and also covers existing PCA82C250 and PCA82C251 applications
• The TJA1042T/3 and TJA1042TK/3 allow for direct interfacing to microcontrollers with
supply voltages down to 3 V
7.1 Operating modes
The TJA1042 supports two operating modes, Normal and Standby, which are selected via
pin STB. See Table 4 for a description of the operating modes under normal supply
conditions.
Table 4. Operating modes
Mode
Pin STB
Normal
Standby
LOW
HIGH
Pin RXD
LOW
bus dominant
wake-up request
detected
HIGH
bus recessive
no wake-up request
detected
7.1.1 Normal mode
A LOW level on pin STB selects Normal mode. In this mode, the transceiver can transmit
and receive data via the bus lines CANH and CANL (see Figure 1 for the block diagram).
The differential receiver converts the analog data on the bus lines into digital data which is
output to pin RXD. The slopes of the output signals on the bus lines are controlled
internally and are optimized in a way that guarantees the lowest possible EME.
7.1.2 Standby mode
A HIGH level on pin STB selects Standby mode. In Standby mode, the transceiver is not
able to transmit or correctly receive data via the bus lines. The transmitter and
Normal-mode receiver blocks are switched off to reduce supply current, and only a
low-power differential receiver monitors the bus lines for activity. The wake-up filter on the
output of the low-power receiver does not latch bus dominant states, but ensures that only
bus dominant and bus recessive states that persist longer than tfltr(wake)bus are reflected on
pin RXD.
In Standby mode, the bus lines are biased to ground to minimize the system supply
current. The low-power receiver is supplied by VIO, and is capable of detecting CAN bus
activity even if VIO is the only supply voltage available. When pin RXD goes LOW to signal
a wake-up request, a transition to Normal mode will not be triggered until STB is forced
LOW.
TJA1042
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 15 January 2015
© NXP N.V. 2015. All rights reserved.
5 of 23
5 Page 
NXP Semiconductors
TJA1042
High-speed CAN transceiver with Standby mode
[6] For TJA1042T/3 and TJA1042TK/3: values valid when VIO = 4.5 V to 5.5 V; when VIO = 2.8 V to 4.5 V, values valid when
Vcm(CAN) = 12 V to +12 V.
11. Dynamic characteristics
Table 8. Dynamic characteristics
Tvj = 40 C to +150 C; VCC = 4.5 V to 5.5 V; VIO = 2.8 V to 5.5 V[1]; RL = 60 unless specified otherwise. All voltages are
defined with respect to ground. Positive currents flow into the IC.[2]
Symbol
Parameter
Conditions
Min Typ Max Unit
Transceiver timing; pins CANH, CANL, TXD and RXD; see Figure 4 and Figure 8
td(TXD-busdom)
td(TXD-busrec)
td(busdom-RXD)
td(busrec-RXD)
tPD(TXD-RXD)
delay time from TXD to bus dominant
delay time from TXD to bus recessive
delay time from bus dominant to RXD
delay time from bus recessive to RXD
propagation delay from TXD to RXD
Normal mode
Normal mode
Normal mode
Normal mode
version with SPLIT pin;
Normal mode
- 65
-
ns
- 90
-
ns
- 60
-
ns
- 65
-
ns
60 -
220 ns
versions with VIO pin;
Normal mode
60 -
250 ns
tbit(RXD)
tto(dom)TXD
tto(dom)bus
tfltr(wake)bus
bit time on pin RXD
TXD dominant time-out time
bus dominant time-out time
bus wake-up filter time
tbit(TXD) = 500 ns
VTXD = 0 V; Normal mode
Standby mode
version with SPLIT pin
Standby mode
[3] 400
0.3
0.3
0.5
-
2
2
1
550 ns
5 ms
5 ms
3 s
versions with VIO pin
Standby mode
0.5 1.5
5
s
td(stb-norm)
standby to normal mode delay time
7 25
47
s
[1] Only TJA1042T/3 and TJA1042TK/3 have a VIO pin. With TJA1042T, the VIO input is internally connected to VCC.
[2] All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to
cover the specified temperature and power supply voltage range.
[3] See Figure 5.
TJA1042
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 15 January 2015
© NXP N.V. 2015. All rights reserved.
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