PDF MAX3673 Data sheet ( Hoja de datos )

Número de pieza	MAX3673
Descripción	Low-Jitter Frequency Synthesizer
Fabricantes	Maxim Integrated Products
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No Preview Available ! 19-4442; Rev 0; 2/09 www.DataSheet4U.com EVAALVUAAILTAIOBNLEKIT Low-Jitter Frequency Synthesizer with Selectable Input Reference General Description The MAX3673 is a low-jitter frequency synthesizer that accepts two reference clock inputs and generates nine phase-aligned outputs. The device features 40kHz jitter transfer bandwidth, 0.3psRMS (12kHz to 20MHz) inte- grated phase jitter, and best-in-class power-supply noise rejection (PSNR), making it ideal for jitter clean- up, frequency translation, and clock distribution in wire- less base-station applications. The MAX3673 operates from a single +3.3V supply and typically consumes 400mW. The IC is available in an 8mm x 8mm, 56-pin TQFN package, and operates from -40°C to +85°C. Applications 3G Wireless Base Stations Frequency Translation Jitter Cleanup Clock Distribution Pin Configuration and Typical Application Circuits appear at end of data sheet. Features ♦ Two Reference Clock Inputs: LVPECL ♦ Nine Phase-Aligned Clock Outputs: LVPECL ♦ Input Frequencies: 61.44MHz,122.88MHz, 245.76MHz, 307.2MHz ♦ Output Frequencies: 61.44MHz, 122.88MHz, 153.6MHz, 245.76MHz, 307.2MHz ♦ Low-Jitter Generation: 0.3psRMS (12kHz to 20MHz) ♦ Clock Failure Indicator for Both Reference Clocks ♦ External Feedback Provides Zero-Delay Capability ♦ Low Output Skew: 20ps Typical Ordering Information PART TEMP RANGE PIN-PACKAGE MAX3673ETN+ -40°C to +85°C 56 TQFN-EP* +Denotes a lead(Pb)-free/RoHS-compliant package. EP = Exposed pad. Functional Diagram REFCLK0 REFCLK0 REFCLK1 REFCLK1 IN0FAIL IN1FAIL LOCK MR SEL_CLK DM CPLL 0.1μF 0 DIV M PFD 1 61.44MHz CREG 0.22μF DA PLL_BYPASS OUTA_EN CP VCO 2.457GHz DIV A 1 0 SIGNAL QUALIFIER AND LOCK DETECT POWER-ON RESET (POR) DIV N DIV B 1 0 MAX3673 10 OUTA3 OUTA3 OUTA2 OUTA2 OUTA1 OUTA1 OUTA0 OUTA0 OUTB_EN OUTB4 OUTB4 OUTB3 OUTB3 OUTB2 OUTB2 OUTB1 OUTB1 OUTB0 OUTB0 FB_SEL FB_IN FB_IN DB ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 page www.DataSheet4U.com Low-Jitter Frequency Synthesizer with Selectable Input Reference INRUSH CURRENT (mA) IOVERSHOOT Figure 1. LVPECL Input Inrush Current IDC t VCC REFCLK0 POWER-ON-RESET (~ 20μs) REFCLK1 OUTxx IN0FAIL HIGH IN1FAIL HIGH LOCK SEL_CLK LOW Figure 2. Power-Up, PLL Locks to REFCLK0 tLOCK (~ 600μs) PLL LOCKED TO REFCLK0 _______________________________________________________________________________________ 5 5 Page www.DataSheet4U.com Low-Jitter Frequency Synthesizer with Selectable Input Reference Table 1. Divider M Configuration for Input Frequencies CONNECTION FROM DM PIN GND VCC Open 10k to GND INPUT FREQUENCY (MHz) 61.44 122.88 245.76 307.2 Table 2. Divider A Configuration for A-Group Output Frequencies CONNECTION FROM DA PIN GND VCC Open 10k to GND OUTPUT FREQUENCY AT OUTA[3:0] (MHz) 61.44 122.88 153.6 307.2 Table 3. Divider B Configuration for B-Group Output Frequencies CONNECTION FROM DB PIN GND VCC Open 10k to GND OUTPUT FREQUENCY AT OUTB[4:0] (MHz) 61.44 122.88 245.76 307.2 Table 4. OUTA[3:0] Enable Control PLL Out-of-Lock Condition If the frequency difference between the reference clock input and the VCO at the PFD input becomes within 500ppm, the PLL is considered to be in lock (LOCK = 0). When the frequency difference between the refer- ence clock input and the VCO at the PFD input becomes greater than 800ppm, the PLL is considered out-of-lock. It should be noted that the LOCK indicator is not part of the frequency qualification used for the INxFAIL indicators. Input and Output Frequencies The MAX3673 input and output dividers are configured using four-level control inputs DM, DA, and DB. Each divider is independent and can have a unique setting. The input connection and associated frequencies are listed in Tables 1, 2, and 3. Output-Enable Controls Each output group (A and B) has a three-level control input OUTA_EN and OUTB_EN. See Tables 4 and 5 for configuration settings. When clock outputs are dis- abled, they are high impedance. Unused enabled out- puts should be left open. Power-On-Reset (POR) At power-on, an internal signal is generated to hold the MAX3673 in a reset state. This internal reset time is about 20µs after VCC reaches 3.0V (Figure 2). During the POR time, the outputs are held to logic-low (OUTxx = low and OUTxx = high). See Table 6 for output signal status during POR. After this internal reset time, the PLL starts to lock to the reference clock selected by SEL_CLK. CONNECTION FROM OUTA_EN PIN A-GROUP OUTPUT ENABLED A-GROUP OUTPUT DISABLED TO HIGH IMPEDANCE GND OUTA0, OUTA1, OUTA2, OUTA3 — VCC — OUTA0, OUTA1, OUTA2, OUTA3 Open OUTA0, OUTA1 OUTA2, OUTA3 Connecting both OUTA_EN and OUTB_EN to VCC enables a factory test mode and forces all indicators to GND. This is not a valid mode of operation. Table 5. OUTB[4:0] Enable Control CONNECTION FROM OUTB_EN PIN B-GROUP OUTPUT ENABLED B-GROUP OUTPUT DISABLED TO HIGH IMPEDANCE GND OUTB0, OUTB1, OUTB2, OUTB3, OUTB4 — VCC OUTB0 OUTB1, OUTB2, OUTB3, OUTB4 Open OUTB0, OUTB1, OUTB2 OUTB3, OUTB4 *Connecting both OUTA_EN and OUTB_EN to VCC enables a factory test mode and forces all indicators to GND. This is not a valid mode of operation. ______________________________________________________________________________________ 11 11 Page

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