PDF TC55VBM316AFTN Data sheet ( Hoja de datos )

Número de pieza	TC55VBM316AFTN
Descripción	MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
Fabricantes	Toshiba Semiconductor
Logotipo
Hay una vista previa y un enlace de descarga de TC55VBM316AFTN (archivo pdf) en la parte inferior de esta página. Total 15 Páginas
No Preview Available ! TC55VBM316AFTN/ASTN40,55 www.DaTtaESNheTeAt4TUI.VcoEm TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 524,288-WORD BY 16-BIT/1,048,576-WORD BY 8-BIT FULL CMOS STATIC RAM DESCRIPTION The TC55VBM316AFTN/ASTN is a 8,388,608-bit static random access memory (SRAM) organized as 524,288 words by 16 bits/1,048,576 words by 8 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 2.3 to 3.6 V power supply. Advanced circuit technology provides both high speed and low power at an operating current of 3 mA/MHz and a minimum cycle time of 40 ns. It is automatically placed in low-power mode at 0.7 µA standby current (at VDD = 3 V, Ta = 25°C, typical) when chip enable ( CE1 ) is asserted high or (CE2) is asserted low. There are three control inputs. CE1 and CE2 are used to select the device and for data retention control, and output enable ( OE ) provides fast memory access. Data byte control pin ( LB , UB ) provides lower and upper byte access. This device is well suited to various microprocessor system applications where high speed, low power and battery backup are required. And, with a guaranteed operating extreme temperature range of −40° to 85°C, the TC55VBM316AFTN/ASTN can be used in environments exhibiting extreme temperature conditions. The TC55VBM316AFTN/ASTN is available in a plastic 48-pin thin-small-outline package (TSOP). FEATURES • Low-power dissipation Operating: 9 mW/MHz (typical) • Single power supply voltage of 2.3 to 3.6 V • Power down features using CE1 and CE2 • Data retention supply voltage of 1.5 to 3.6 V • Direct TTL compatibility for all inputs and outputs • Wide operating temperature range of −40° to 85°C • Standby Current (maximum): 3.6 V 3.0 V 10 µA 5 µA PIN ASSIGNMENT (TOP VIEW) 48 PIN TSOP 1 48 24 25 (Normal) • Access Times (maximum): TC55VBM316AFTN/ASTN 40 55 Access Time 40 ns 55 ns CE1 Access Time 40 ns 55 ns CE2 Access Time 40 ns 55 ns OE Access Time 25 ns 30 ns • Package: TSOP 48-P-1220-0.50 (AFTN) (Weight:0.51 g typ) TSOP 48-P-1214-0.50 (ASTN) (Weight:0.36 g typ) PIN NAMES A0~A18 A-1~A18 CE1 , CE2 R/W OE LB , UB I/O1~I/O16 BYTE VDD GND NC OP* Address Inputs (Word Mode) Address Inputs (Byte Mode) Chip Enable Read/Write Control Output Enable Data Byte Control Data Inputs/Outputs Byte (×8 mode) Enable Power Ground No Connection Option *: OP pin must be open or connected to GND. Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A15 A14 A13 A12 A11 A10 A9 A8 NC NC R/W CE2 OP UB LB A18 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 A17 A7 A6 A5 A4 A3 A2 A1 A0 CE1 GND OE I/O1 I/O9 I/O2 I/O10 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 I/O3 I/O11 I/O4 I/O12 VDD I/O5 I/O13 I/O6 I/O14 I/O7 I/O15 I/O8 I/O16 GND /A-1 BYTE A16 2002-08-05 1/15 1 page TC55VBM316AFTN/ASTN40,55 www.DaAtaCSheCetH4UA.cRomACTERISTICS AND OPERATING CONDITIONS (Ta = −40° to 85°C, VDD = 2.7 to 3.6 V) READ CYCLE SYMBOL PARAMETER tRC tACC tCO1 tCO2 tOE tBA tCOE tOEE tBE tOD tODO tBD tOH Read Cycle Time Address Access Time Chip Enable( CE1 ) Access Time Chip Enable(CE2) Access Time Output Enable Access Time Data Byte Control Access Time Chip Enable Low to Output Active Output Enable Low to Output Active Data Byte Control Low to Output Active Chip Enable High to Output High-Z Output Enable High to Output High-Z Data Byte Control High to Output High-Z Output Data Hold Time TC55VBM316AFTN/ASTN 40 55 MIN MAX MIN MAX 40  55   40  55  40  55  40  55  25  30  40  55 55 00 55  20  25  20  25  20  25 10  10  UNIT ns WRITE CYCLE TC55VBM316AFTN/ASTN SYMBOL PARAMETER 40 55 UNIT MIN MAX MIN MAX tWC Write Cycle Time 40  55  tWP Write Pulse Width 30  40  tCW Chip Enable to End of Write 35  45  tBW Data Byte Control to End of Write 35  45  tAS Address Setup Time tWR Write Recovery Time 00 ns 00 tODW R/W Low to Output High-Z  20  25 tOEW R/W High to Output Active 00 tDS Data Setup Time 20  25  tDH Data Hold Time 00 Note: tOD, tODO, tBD and tODW are specified in time when an output becomes high impedance, and are not judged depending on an output voltage level. 2002-08-05 5/15 5 Page TC55VBM316AFTN/ASTN40,55 www.DaDtaSAhTeeAt4UR.cEomTENTION CHARACTERISTICS (Ta = −40° to 85°C) SYMBOL PARAMETER VDH IDDS2 tCDR tR Data Retention Supply Voltage Standby Current VDH = 3.6 V Ta = −40~85°C Ta = −40~40°C VDH = 3.0 V Ta = −40~85°C Chip Deselect to Data Retention Mode Time Recovery Time MIN 1.5    0 5 TYP       MAX 3.6 10 2 5   UNIT V µA ns ms CE1 CONTROLLED DATA RETENTION MODE (See Note 1) VDD VDD 2.3 V DATA RETENTION MODE VIH CE1 (See Note 2) tCDR VDD − 0.2 V GND CE2 CONTROLLED DATA RETENTION MODE (See Note 3) VDD VDD DATA RETENTION MODE 2.3 V CE2 VIH tCDR VIL 0.2 V GND UB , LB CONTROLLED DATA RETENTION MODE (See Note 4) VDD VDD 2.3 V DATA RETENTION MODE (See Note 2) tR tR VIH UB , LB GND (See Note 5) tCDR VDD − 0.2 V (See Note 5) tR 2002-08-05 11/15 11 Page

Páginas	Total 15 Páginas
PDF Descargar	[ Datasheet TC55VBM316AFTN.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
TC55VBM316AFTN	MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS	Toshiba Semiconductor

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar