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PDF DRPIC1655X Data sheet ( Hoja de datos )
| Número de pieza | DRPIC1655X | |
| Descripción | High Performance Configurable 8-bit RISC Microcontroller | |
| Fabricantes | Digital Core Design | |
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DRPIC1655X
High Performance Configurable
8-bit RISC Microcontroller
ver 2.15
OVERVIEW
The DRPIC1655X is a low-cost, high per-
formance, 8-bit, fully static soft IP Core,
dedicated for operation with fast (typically on-
chip) dual ported memory. The core has been
designed with a special concern about low
power consumption.
DRPIC1655X soft core is software-
compatible with the industry standard
PIC16C554 and PIC16C558. It implements an
enhanced Harvard architecture (i.e.
separate instruction and data memories) with
independent address and data buses. The 14
bit program memory and 8-bit dual port data
memory allow instruction fetch and data
operations to occur simultaneously. The
advantage of this architecture is that
instruction fetch and memory transfers can be
overlapped by multi stage pipeline, so that the
next instruction can be fetched from program
memory while the current instruction is
executed with data from the data memory.
The DRPIC1655X architecture is 4 times
faster compared to standard architecture. So
most instructions are executed within 1
system clock period, except the instructions
which directly operates on program counter
PC (GOTO, CALL, RETURN), this situation
require the pipeline to be cleared and
subsequently refilled. This operation takes
additional one clock cycle.
The DRPIC1655X Microcontroller fits
perfectly in applications ranging from high-
All trademarks mentioned in this document
are trademarks of their respective owners.
speed automotive and appliance motor control
to low-power remote transmitters/receivers,
pointing devices and telecom processors.
Built-in power save mode make this IP perfect
for applications where power consumption is
critical.
DRPIC1655X is delivered with fully
automated testbench and complete set of
tests allowing easy package validation at
each stage of SoC design flow
CPU FEATURES
● Software compatible with industry standard
PIC16C55X
● Pipelined Harvard architecture 4 times
faster compared to original implementation
● 35 instructions
● 14 bit wide instruction word
● Up to 32 K bytes of internal Data Memory
● Up to 64K bytes of Program Memory
● Configurable hardware stack
● Power saving SLEEP mode
● Fully synthesizable, static synchronous
design with no internal tri-states
● Technology independent HDL Source
Code
● 1.4 GHz virtual clock frequency in a 0.18u
technological process
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
1 page  
www.DWataaStchehedt4oUg.comTimer– it’s a free running timer.
WDT has own clock input separate from
system clock. It means that the WDT will run
even if the system clock is stopped by
execution of SLEEP instruction. During normal
operation, a WDT time-out generates a
Watchdog reset. If the device is in SLEEP
mode the WDT time-out causes the device to
wake-up and continue with normal operation.
I/O Ports – Block contains DRPIC1655X’s
general purpose I/O ports and data direction
registers (TRIS). The DRPIC1655X has four
8-bit full bi-directional ports PORT A, PORT B,
PORT C, PORT D. Each port’s bit can be
individually accessed by bit addressable
instructions. Read and write accesses to the
I/O port are performed via their corresponding
SFR’s PORTA, PORTB, PORTC, PORTD.
The reading instruction always reads the
status of Port pins. Writing instructions always
write into the Port latches. Each port’s pin has
an corresponding bit in TRISA, B, C and D
registers. When the bit of TRIS register is set
this means that the corresponding bit of port is
configured as an input (output drivers are set
into the High Impedance).
DoCD™ Debug Unit – it’s a real-time
hardware debugger provides debugging
capability of a whole SoC system. In contrast
to other on-chip debuggers DoCD™ provides
non-intrusive debugging of running
application. It can halt, run, step into or skip
an instruction, read/write any contents of
microcontroller including all registers, internal,
external, program memories, all SFRs
including user defined peripherals. Hardware
breakpoints can be set and controlled on
program memory, internal and external data
memories, as well as on SFRs. Hardware
breakpoint is executed if any write/read
occurred at particular address with certain
data pattern or without pattern. The DoCD™
system includes three-wire interface and
complete set of tools to communicate and
work with core in real time debugging. It is
built as scalable unit and some features can
be turned off to save silicon and reduce power
consumption. A special care on power
consumption has been taken, and when
debugger is not used it is automatically
switched in power save mode. Finally whole
debugger is turned off when debug option is
no longer used.
OPTIONAL
PERIPHERALS
There are also available an optional
peripherals, not included in presented
DRPIC1655X Microcontroller Core. The
optional peripherals, can be implemented in
microcontroller core upon customer request.
● Timer 1 and Timer 2
● Full duplex UART
● SPI – Master and Slave Serial Peripheral
Interface
○ Supports speeds up ¼ of system clock
○ Mode fault error
○ Write collision error
○ Software selectable polarity and phase of
serial clock SCK
○ System errors detection
○ Allows operation from a wide range of system
clock frequencies (build-in 5-bit timer)
○ Interrupt generation
● PWM – Pulse Width Modulation Timer
○ 2 independent 8-bit PWM channels,
concatenated on one 16-bit PWM channel
○ Software-selectable duty from 0% to 100% and
pulse period
○ Software-selectable polarity of output
waveform
● I2C bus controller - Master
○ 7-bit and 10-bit addressing modes
○ NORMAL, FAST, HIGH speeds
○ Multi-master systems supported
○ Clock arbitration and synchronization
○ User defined timings on I2C lines
○ Wide range of system clock frequencies
○ Interrupt generation
● I2C bus controller - Slave
○ NORMAL speed 100 kbs
○ FAST speed 400 kbs
○ HIGH speed 3400 kbs
○ Wide range of system clock frequencies
○ User defined data setup time on I2C lines
○ Interrupt generation
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
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| PDF Descargar | [ Datasheet DRPIC1655X.PDF ] | |
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