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PDF FAN9612 Data sheet ( Hoja de datos )
| Número de pieza | FAN9612 | |
| Descripción | Interleaved Dual BCM PFC Controller | |
| Fabricantes | Fairchild Semiconductor | |
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PRELIMINARY
February 2009
FAN9612
Interleaved Dual BCM PFC Controller
Features
Low Total Harmonic Distortion, High Power Factor
180° Out of Phase Synchronization
Automatic Phase Disable at Light Load
1.8A Sink, 0.8A Source, High Current Gate Drivers
Trans-conductance (gM) Error Amplifier
Voltage-Mode Control with (VIN)2 Feed Forward
Closed-Loop Soft-Start with User-Programmable
Soft-Start Time for Reduced Overshoot
Minimum Restart Timer Frequency to Avoid Audible
Noise
Maximum Switching Frequency Clamp
Brown-Out Protection with Soft-Recovery
Non-Latching OVP on FB pin and Latching Second
Level Protection on OVP Pin
Open Feedback Protection
Over-Current & Power-Limit Protection for Each
Phase
Low Start-Up Current of 80-µA Typical
Works with DC, 50Hz to 400Hz ac Inputs
Applications
100-1000W Off-line Power Supplies
Large Screen LCD-TV, PDP-TV, RP-TV Power
High-End Desktop PC and Server Power Supplies
80-PLUS Certified Equipment
Description
The FAN9612 Interleaved Dual Boundary-Conduction-
Mode (BCM) Power-Factor-Correction Controller
operates two parallel-connected boost power trains 180º
out of phase. Interleaving extends the maximum
practical power level of the control technique from about
300W to greater than 800W. Unlike the continuous
conduction mode (CCM) technique often used at higher
power levels, BCM offers inherent zero-current switching
of the boost diodes (no reverse-recovery losses), which
permits the use of less expensive diodes without
sacrificing efficiency. Furthermore, the input and output
filters can be made smaller due to ripple current
cancellation and effective doubling of the switching
frequency.
The converters operate with variable frequency which is
a function of the load and the instantaneous input /
output voltages. The switching frequency is limited
between 18kHz and 600kHz. The Pulse Width
Modulators implement voltage-mode control with input
voltage feed forward. When configured for PFC
applications, the slow voltage regulation loop results in
constant on-time operation within a line cycle. This PWM
method combined with the BCM operation of the boost
converters provides automatic power factor correction.
The FAN9612 offers bias UVLO, input brown-out, input
over-voltage, over-current, open feedback, over-
temperature, output over-voltage and redundant latching
over-voltage protections. Furthermore, the converters’
output power is limited independently of the input RMS
voltage. Synchronization between the power stages is
maintained under all operating conditions. The FAN9612
is available in Lead(Pb)-Free 16-lead SOIC package.
Simplified Application Diagram
© 2008 Fairchild Semiconductor Corporation
FAN9612 • Rev. 0.9.1E
www.fairchildsemi.com
1 page  
www.DataSheet4U.com
Pin Definitions
Pin#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Name
ZCD1
ZCD2
5VB
MOT
AGND
SS
COMP
FB
OVP
VIN
PGND
DRV2
DRV1
VDD
CS2
CS1
PRELIMINARY
Pin Description
Zero current detector for Phase 1 of the interleaved boost power stage.
Zero current detector for Phase 2 of the interleaved boost power stage.
5V Bias. Bypass pin for the internal supply which powers all control circuitry on the IC.
Maximum On-Time adjust for the individual power stages.
Analog Ground. Reference potential for all setup signals.
Soft-Start Capacitor. Connected to the non-inverting input of the error amplifier.
Compensation-Network connection to the output of the gM error amplifier
Feedback pin to sense the converter’s output voltage; inverting input of the error amplifier.
Output Voltage Monitor for the independent second level latched OVP protection.
Input Voltage Monitor for brown-out protection and input voltage feed forward.
Power Ground connection.
Gate Drive Output for Phase 2 of the interleaved boost power stage.
Gate Drive Output for Phase 1 of the interleaved boost power stage.
External Bias Supply for the IC.
Current Sense Input for Phase 2 of the interleaved boost power stage.
Current Sense Input for Phase 1 of the interleaved boost power stage.
© 2008 Fairchild Semiconductor Corporation
FAN9612 • Rev. 0.9.1E
5
www.fairchildsemi.com
5 Page 
www.DataSheet4U.com
PRELIMINARY
The pulse width modulator of the FAN9612 implements
voltage mode control. This control method compares an
artificial ramp to the output of the error amplifier to
determine the desired on-time of the converter’s power
transistor to achieve output voltage regulation.
VRAMP1 VRAMP2
VCONTROL
Figure 6. Interleaved PFC Boost Operation
Parallel power processing is penalized by the increased
number of power components but offers significant
benefits to keep current and thermal stresses under
control and to increase the power handling capability of
the otherwise limited solution using BCM control
method for boost power factor correction. Furthermore,
the switches of the two boost converters can be
operated 180 degrees out of phase from each other.
The control of parallel converters operating 180
degrees out of phase is called interleaving. Interleaving
provides considerable ripple current reduction at the
input and output terminals of the power supply which
favorably affects the input EMI filter requirements and
reduces the high frequency RMS current of the output
capacitor of the power supply.
There is an obvious difficulty to interleave two BCM
boost converters. Since the converter’s operating
frequency is influenced by component tolerances in the
power stage and in the controller as well, the two
converters will operate at different frequencies.
Therefore special attention must be paid to ensure that
the two converters will be locked in to 180 degrees out
of phase operation. Consequently, synchronization is a
critical function of an interleaved boundary conduction
mode PFC controller and it is implemented in the
FAN9612 using a dedicated circuitry.
3. Voltage Regulation, Voltage Mode Control
The power supply’s output voltage is regulated by a
negative feedback loop and a pulse width modulator.
The negative feedback is provided by an error amplifier
which compares the feedback signal at the inverting
input to a reference voltage connected to the non-
inverting input of the amplifier. Similarly to other PFC
applications, the error amplifier is compensated with
high DC gain for accurate voltage regulation but very
low bandwidth to suppress line frequency ripple present
across the output capacitor of the converter. The line
frequency ripple is the result of the constant output
power of the converter and the fact that the input power
is the product of a sinusoidal current and a sinusoidal
voltage thus follows a sine square function. Eliminating
the line frequency component from the feedback
system is imperative to maintain low total harmonic
distortion (THD) in the input current waveform.
PWM1
PWM2
t
Figure 7. FAN9612 PWM Operation
In the FAN9612 there are two PWM sections
corresponding to the two parallel power stages. For
proper interleaved operation two independent 180
degrees out of phase ramps are needed which
necessitates the two pulse width modulators. To ensure
that the two converters process the same amount of
power the artificial ramps have the same slope and they
use the same control signal generated by the error
amplifier.
4. Input-Voltage Feed-Forward
Basic voltage mode control, as described in the
previous section, provides satisfactory regulation
performance in most cases. One important
characteristic of the technique is that input voltage
variation to the converter requires a corrective action
from the error amplifier to maintain the output at the
desired voltage. When the error amplifier has adequate
bandwidth like in most DC-DC applications, it is able to
maintain regulation within a tolerable output voltage
range during input voltage changes.
On the other hand, when voltage-mode control is used
in power factor corrector applications, the error amplifier
bandwidth and its capability to quickly react to input
voltage changes, is severely limited. In these cases the
input voltage variation can easily cause excessive
overshoot or droop at the converter output as the input
voltage goes up or down respectively.
To overcome this shortcoming of the voltage mode
PWM circuit in PFC applications, input-voltage feed-
forward is often employed. It can be shown
mathematically that a PWM ramp proportional to the
square of the input voltage will inherently reject the
effect of input voltage variations on the output voltage
and will eliminate the need of any correction by the error
amplifier.
© 2008 Fairchild Semiconductor Corporation
FAN9612 • Rev. 0.9.1E
11
www.fairchildsemi.com
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| PDF Descargar | [ Datasheet FAN9612.PDF ] | |
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