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PDF DAC667 Data sheet ( Hoja de datos )
| Número de pieza | DAC667 | |
| Descripción | Microprocessor-Compatible 12-BIT DIGITAL-TO-ANALOG CONVERTER | |
| Fabricantes | Burr-Brown Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de DAC667 (archivo pdf) en la parte inferior de esta página. Total 9 Páginas | ||
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www.DataSheet4U.com
®
DAC667
DAC667
Microprocessor-Compatible
12-BIT DIGITAL-TO-ANALOG CONVERTER
FEATURES
q ±3/4LSB MAX NONLINEARITY OVER
TEMPERATURE
q MONOTONICITY GUARANTEED OVER
TEMPERATURE
q MICROCOMPUTER INTERFACE:
Double-Buffered Latch
q VOLTAGE OUTPUT: ±10V, ±5V, +10V
With ±12V to ±15V Supplies
q LOW POWER DISSIPATION: 345mW typ
q PIN COMPATIBLE WITH AD667
DESCRIPTION
The DAC667 is a complete monolithic integrated cir-
cuit microprocessor-compatible 12-bit digital-to-ana-
log converter. It includes a precision voltage reference,
microcomputer interface logic, double-buffered latch,
and a 12-bit D/A converter with a voltage output
amplifier. Fast current switches and a laser-trimmed
thin-film resistor network provide a highly accurate
and fast D/A converter.
A double-buffered latch facilitates microcomputer inter-
facing to 4-, 8-, 12-, or 16-bit data buses. The input
buffer latch holds the 12-bit data until it is transferred
to an internal 12-bit D/A converter latch, giving precise
timing control over an analog output change.
The DAC667 is specified to ±1/2LSB maximum lin-
earity error at +25°C. The DAC667 is guaranteed
monotonic over the specification temperature range.
The DAC667 is available in 28-pin, 0.6" wide plastic
DIP package.
+VCC
8
Power Gnd
16
–VEE
10
Ref Out 6
Ref In 7
19.95kΩ
Reference
12-Bit D/A Converter
A3 12
A0 15
12-Bit Parallel Latch
A1 14
A2 13
CS 11
4 Bits
4 Bits
4 Bits
9.95kΩ
28 27 26 25 24 23 22 21 20 19 18 17
DB11 • • • • • • • • • • • • • • • • • • • DB0
MSB
LSB
5kΩ
5kΩ
1 20V Span
2 10V Span
3
Summing
Junction
9 VOUT
5 AGND
4 Bipolar
Offset
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1990 Burr-Brown Corporation
PDS-11091C
DAC667Printed in U.S.A. March, 1998
®
1 page  
www.DataSheezt4eUro.coamnalog output and all ones (FFFHEX) gives an analog
output 1LSB below full scale.
Input coding for bipolar analog outputs is bipolar offset
binary (BOB), where an input code of 000HEX gives a minus
full-scale output, an input of FFFHEX gives an output 1LSB
below positive full scale, and zero occurs for an input code
of 800HEX.
The DAC667 can be used with two’s complement coding if
a logic inverter is used ahead of the MSB input (DB11).
INTERNAL/EXTERNAL REFERENCE USE
DAC667 contains a +10V reference which is trimmed to
typically ±0.2% and tested and guaranteed to ±1%. VREF OUT
must be connected to VREF IN through a gain adjust resistor
with a nominal value of 50Ω. A trim potentiometer with a
nominal value of 100Ω can be used to provide adjustment to
zero gain error. If an external 10.000V reference is used, it
may be necessary to increase the trim range slightly.
The reference output may be used to drive external loads,
sourcing up to 5mA. The load current should be constant,
otherwise the gain (and bipolar offset, if connected) of the
converter will vary.
It is possible to use references other than +10V. The recom-
mended range of reference voltage is from +8V to +11V,
which allows both 8.192V and 10.24V ranges to be used.
The DAC667 is optimized for fixed-reference applications.
If the reference voltage is expected to vary over a wide
range, a CMOS multiplying D/A is a better choice.
GAIN AND OFFSET ADJUSTMENTS
Figures 2 and 3 illustrate the relationship of offset and gain
adjustments to a unipolar- and a bipolar-connected DAC667.
Offset should be adjusted first to avoid interaction of adjust-
ments.
1LSB
+ Full Scale
Range of
Gain Adj.
≈ ±1%
Gain Adjust
Rotates the Line
+ Full Scale
1LSB
All Bits
Logic 0
Full Scale
Range
Range of
Gain Adj.
≈ ±1%
Gain Adjust
Rotates the Line
Range of
Offset Adjust
Offset Adj.
Translates
the Line
≈ ±0.4%
Bipolar
Offset
MSB on All
Others Off
All Bits
Logic 1
Digital Input
– Full Scale
FIGURE 3. Relationship of Offset and Gain Adjustments for
a Bipolar D/A Converter.
Offset Adjustment
For unipolar (USB) operation, apply the digital input code
that should produce zero voltage output and adjust the offset
potentiometer for zero output. For bipolar (BOB, BTC)
operation, apply the digital input code that produces the
maximum negative output voltage and adjust the offset
potentiometer for minus full scale voltage. See Table II for
calibration values and codes.
DIGITAL
INPUT 0 to +5V
FFFHEX
800HEX
7FFHEX
000HEX
1LSB
+4.9987V
+2.5000V
+2.4987V
0.0000V
1.22mV
ANALOG OUTPUT
0 to +10V ±2.5V
±5V
+9.9976V
+5.0000V
+4.9976V
0.0000V
2.44mV
+2.4987V
0.0000V
–0.0013V
–2.5000V
1.22mV
+4.9976V
0.0000V
–0.0024V
–5.0000V
2.44mV
±10V
+9.9951V
0.0000V
–0.0049V
–10.0000V
4.88mV
TABLE II. Calibration Values.
Gain Adjustment
For either unipolar or bipolar operation, apply the digital
input that gives the maximum positive voltage output. Ad-
just the gain potentiometer for this positive full scale volt-
age. See Table II for calibration values.
Range of
Offset Adj.
≈ ±0.4%
All Bits
Logic 0
All Bits
Logic 1
Digital Input
Offset Adjust Translates the Line
FIGURE 2. Relationship of Offset and Gain Adjustments for
a Unipolar D/A Converter.
SETTLING TIME
PERFORMANCE
The switches, reference and output amplifier of the DAC667
are designed for optimum settling time performance (Figure
4). Figure 4a shows the full scale range step response, VOUT
–10V to +10V to –10V, for data input 000HEX to FFFHEX to
000HEX. Figure 4b shows the settling time response at plus
full scale (+10V) for an output transition from –10V to
+10V. Figure 4c shows the settling time response at minus
®
5 DAC667
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet DAC667.PDF ] | |
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