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Zarlink Semiconductor - SyncE SONET/SDH Line Card PLL

Numéro de référence ZL30146
Description SyncE SONET/SDH Line Card PLL
Fabricant Zarlink Semiconductor 
Logo Zarlink Semiconductor 





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ZL30146 fiche technique
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ZL30146
SyncE SONET/SDH Line Card PLL
Features
• Synchronizes to standard telecom or Ethernet
backplane clocks and provides jitter filtered output
clocks for SONET/SDH, PDH and Ethernet network
interface cards
• Supports the requirements of ITU-T G.8262 for
synchronous Ethernet Equipment slave Clocks
• Meets the SONET/SDH jitter generation
requirements up to OC-192/STM-64
• Two independent DPLLs provides timing for the
transmit path (backplane to line rate) and the
receive path (recovered line rate to backplane)
• Synchronizes to telecom reference clocks (2 kHz,
N*8 kHz up to 77.76 MHz, 155.52 MHz) or to
Ethernet reference clocks (25 MHz, 50 MHz,
62.5 MHz, 125 MHz)
• Selectable loop bandwidth of 14 Hz, 28 Hz, 890 Hz,
3.5 Hz, 1.7 Hz, or 0.1 Hz
• Supports automatic hitless reference switching and
short term holdover during loss of reference inputs
• Generates standard SONET/SDH clock rates (e.g.,
19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz,
622.08 MHz) or Ethernet clock rates (e.g., 25 MHz,
50 MHz, 125 MHz, 156.25 MHz, 312.5 MHz) for
synchronizing Ethernet PHYs
Short Form Data Sheet
February 2009
Ordering Information
ZL30146GGG 64 Pin CABGA
ZL30146GGG2 64 Pin CABGA*
*Pb Free Tin/Silver/Copper
-40oC to +85oC
Trays
Trays
• Programmable output synthesizer to generate
telecom clock frequencies from any multiple of
8 kHz up to 100 MHz (e.g., T1/E1, DS3/E3)
• Generates several styles of output frame pulse
with selectable pulse width, polarity, and frequency
• Configurable input to output delay and output to
output phase alignment
• Configurable through a serial interface (SPI or I2C)
• DPLLs can be configured to provide synchronous
or asynchronous clock outputs
Applications
• ITU-T G.8262 Line Cards which support 1 GbE
and 10 GbE interfaces
• SONET/SDH line cards up to OC-192/STM-64
osci
osco
ref0
ref1
ref2
ref3
ref4
sync0
Input
Ports
Ref/Sync
Monitors
refm Rx DPLL
refn/syncn
Tx DPLL
P rogram m able
S yn th e s iz e r
N*8kHz
p_clk
p_fp
Ethernet/
SONET
APLL
diff
apll_clk
mode hold lock
I2C/SPI
JTAG
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2009, Zarlink Semiconductor Inc. All Rights Reserved.

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