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PDF IP1001LF Data sheet ( Hoja de datos )
| Número de pieza | IP1001LF | |
| Descripción | Integrated 10/100/1000 Gigabit Ethernet Transceiver | |
| Fabricantes | IC Plus | |
| Logotipo |  |
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IP1001 LF
Data Sheet
Integrated 10/100/1000 Gigabit Ethernet Transceiver
Features
IEEE 802.3 compliant 1000BASE-T,
100BASE-TX, and 10BASE-T
Support auto-negotiation
Support timing programmable MII/ GMII/
RGMII (delay clock, and driving current etc.)
Support 3 power saving modes
Support software based Smart Cable Analyzer
(SCA)
Support auto MDI/MDIX (auto negotiation or
force mode)
Support auto polarity correction
Supports programmable LED modes and LED
driving current
Supports speed down shift feature
Built in synchronization FIFO to support jumbo
frame size up to 10KB in giga mode (4KB in
10M/100M mode)
Supports 2.1v and 1.2v built-in regulator
control
Provide a 125MHz free running clock
Operating voltage 3.3v/ (2.5v option for
RGMII)/ 1.8v/ 1.2v
64-pin QFN lead-free package
Supports Lead Free package (Please refer to
the Order Information)
General Description
IP1001 is an integrated physical layer device for
1000BASE-T, 100BASE-TX, and 10BASE-T
applications. IP1001 supports MII, GMII and
RGMII for different types of 10/100/1000Mb Media
Access Controller (MAC). It supports Auto
MDI/MDIX function to simplify the network
installation and reduce the system maintenance
cost. IP1001 supports speed down shift feature for
a poor link quality to guarantee data transmission.
Cable analysis function “SCA” is supported by
programming MII registers of IP1001 through
MDC/MDIO.
IP1001 supports 2 types of power saving modes;
i.e., power down mode defined in IEEE802.3, and
APS (auto power saving).
MAC Device
Physical Layer Device
Network Medium
SNwSNIiwCtcIiC/thc/h
RGMII/ GMII/ MII
IPI1P0100101
TP-MDI
Magnetic
Magnetic
10BASE-T
RJ45
RJ45
100BASE-TX
1000BASE-T
Copyright © 2006, IC Plus Corp.
1/48
Dec. 18, 2007
IP1001-DS-R06
1 page  
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IP1001 LF
Data Sheet
2 Pin description
Abbreviation
Abbreviation
PWR
I
LI
O
I/O
OD
IPH
IPL
IPECL
OPECL
Description
Power and Ground Pin
Schmitt trigger input
The input is latched at the end of reset and used as a default value
Output
Schmitt trigger input/ Output
Open drain output
Schmitt trigger input with 60 kohm internal pull high
Schmitt trigger input with 60 kohm internal pull low
PECL input
PECL output
Copyright © 2006, IC Plus Corp.
5/48
Dec. 18, 2007
IP1001-DS-R06
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www.DataSheet4U.com
IP1001 LF
Data Sheet
Pin description (continued)
Pin no.
Label
LED Display
55 LED_MODE0
15,14,13
LED2, LED1,
LED0
Type Description
LI/O LED Mode Selection (MODE0~MODE3).
LED_MODE[1:0] can provide 4 LED display modes, Mode0~
Mode3.
LED_MODE1 is set by register16[15]. LED_MODE0 is
defined by pin or by register16[14]. The pin state of
LED_MODE0 is latched upon reset and set to register 16[14].
After power up, the designer can configure LED_MODE[1:0]
register during the operation.
Since LED_MODE1 is set to “0” upon reset, the designer can
set pin 55 to select “00” or “01” display mode if the register
16[15:14] is unchanged.
IPH/O, LED output pins 0,1,2
LI/O
LED_Mode1,
LED_Mode0
LED0
LED1
LED2
Mode0
00
10/100M Link/Act
0: link off
1: 10/100M link on
Flash: TX or RX
100M Link/Act
0: link off
1: 100M link on
Flash: TX or RX
1G Link/Act
0: link off
1: Giga link on
Flash: TX or RX
Mode1
Mode2
01 10
Bi-color mode
{LED0, LED1}=
10= 1G Link;
01=10/100M Link;
00= link off
11= link off
Act
0: link off or idle
1: TX or RX
1G Link/Act
0: link off
1: Giga link on
Flash: TX or RX
100M Link/Act
0: link off
1: 100M link on
Flash: TX or RX
10M Link/Act
0: link off
1: 10M link on
Flash: TX or RX
Mode3
11
Bi-triple-color mode
{LED0, LED1}=
10= 1G Link;
01= 100M Link
00= 10M Link;
11= link off
Link/ Act
0: link off
1: 10/100M/giga link
on
Flash: TX or RX
Copyright © 2006, IC Plus Corp.
11/48
Dec. 18, 2007
IP1001-DS-R06
11 Page | ||
| Páginas | Total 48 Páginas | |
| PDF Descargar | [ Datasheet IP1001LF.PDF ] | |
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