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PDF FAN5009 Data sheet ( Hoja de datos )
| Número de pieza | FAN5009 | |
| Descripción | Dual Bootstrapped 12V MOSFET Driver | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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www.fairchildsemi.com
FAN5009
Dual Bootstrapped 12V MOSFET Driver
Features
• Drives N-channel High-Side and Low-Side MOSFETs in
a synchronous buck configuration
• 12V High-Side and 12V Low-Side Drive
• Internal Adaptive “Shoot-Through” Protection
• Integrated Bootstrap Diode for High-Side Drive
• Fast rise and fall times
• Switching Frequency Up to 500kHz
• OD input for Output Disable – allows for synchronization
with PWM controller
• SOIC-8 Package
• Available in low thermal resistance MLP package
Applications
• Multi-phase VRM/VRD regulators for Microprocessor
Power
• High Current/High Frequency DC/DC Converters
• High Power Modular Supplies
General Description
The FAN5009 is a dual, high frequency MOSFET driver,
specifically designed to drive N-Channel power MOSFETs
in a synchronous-rectified buck converter. These drivers,
combined with a Fairchild Multi-Phase PWM controller and
power MOSFETs, form a complete core voltage regulator
solution for advanced microprocessors.
The FAN5009 drives the upper and lower MOSFET gates of
a synchronous buck regulator to 12VGS. The upper gate
drive includes an integrated boot diode and requires only an
external bootstrap capacitor (CBOOT). The output drivers in
the FAN5009 have the capacity to efficiently switch power
MOSFETs at frequencies up to 500kHz. The circuit’s
adaptive shoot-through protection prevents the MOSFETs
from conducting simultaneously.
The FAN5009 is rated for operation from 0°C to +85°C and
is available in low-cost SOIC-8 or MLP packages.
Typical Application
FAN5009
PWM 2
OD
3
OVERLAP
PROTECTION
CIRCUIT
VCC
VCC
4
12V
C VCC
BOOT
1
Q1
8 HDRV
7 SW
Q2
CBOOT
L1
5 LDRV
PGND
6
VOUT
C OUT
Figure 1. Typical Application.
REV. 1.0.5 7/22/04
1 page  
PRODUCT SPECIFICATION
www.DataSheet4U.com
Electrical Specifications (continued)
FAN5009
Parameter
Low-Side Driver
Output Resistance, Sourcing
Current
Output Resistance, Sinking
Current
Transition Times2,4
Propagation Delay2,3
Symbol
Conditions
RLUP
RLDN
tR(LDRV)
tF(LDRV)
tpdh(LDRV)
tpdl(LDRV)
tpdh(ODRV)
See Figure 2
See Figures 2, 4
See Adaptive Gate
Drive Circuit
description
Min. Typ. Max. Units
3.4 4.0 Ω
1.4 1.8 Ω
40 50 ns
20 30 ns
20 30 ns
25 40 ns
240 ns
NOTES:
1. All limits at operating temperature extremes are guaranteed by design, characterization and statistical quality control
2. AC Specifications guaranteed by design/characterization (not production tested).
3. For propagation delays, “tpdh” refers to low-to-high signal transition and “tpdl” refers to high-to-low signal transition
4. Transition times are defined for 10% and 90% of DC values
OD
VIL(OD)
t pdl(OD)
VIH(OD)
t pdh(OD)
LDRV / HDRV
Figure 3. Output Disable Timing
VIH(PWM)
PWM
t pdl (LDRV)
LDRV
1.2V
t pdh(HDRV)
HDRV-SW
VIL(PWM)
t pdl (HDRV)
t pdh(LDRV)
SW
2.2V
REV. 1.0.5 7/22/04
Figure 4. Adaptive Gate Drive Timing
5
5 Page 
PRODUCT SPECIFICATION
www.DataSheet4U.com
Mechanical Dimensions
0.150, 8 Lead SOIC Package
Symbol
A
A1
B
C
D
E
e
H
h
L
N
α
ccc
Inches
Min. Max.
.053 .069
.004 .010
.013 .020
.0075 .010
.189 .197
.150 .158
.050 BSC
.228 .244
.010 .020
.016 .050
8
0° 8°
— .004
Millimeters
Min. Max.
1.35 1.75
0.10 0.25
0.33 0.51
0.20 0.25
4.80 5.00
3.81 4.01
1.27 BSC
5.79 6.20
0.25 0.50
0.40 1.27
8
0° 8°
— 0.10
Notes
5
2
2
3
6
FAN5009
Notes:
1. Dimensioning and tolerancing per ANSI Y14.5M-1982.
2. "D" and "E" do not include mold flash. Mold flash or
protrusions shall not exceed .010 inch (0.25mm).
3. "L" is the length of terminal for soldering to a substrate.
4. Terminal numbers are shown for reference only.
5. "C" dimension does not include solder finish thickness.
6. Symbol "N" is the maximum number of terminals.
85
EH
14
D
A1
A
SEATING – C –
e PLANE LEAD COPLANARITY
B ccc C
α
h x 45°
C
L
REV. 1.0.5 7/22/04
11
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| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet FAN5009.PDF ] | |
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