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PDF NJU26100 Data sheet ( Hoja de datos )
| Número de pieza | NJU26100 | |
| Descripción | Hardware Specification | |
| Fabricantes | New Japan Radio | |
| Logotipo |  |
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NJU26100 Series
NJU26100 Series Hardware Specification
■ General Description
■Package
This document describes the NJU26100 Series common hardware specifications.
This document is applied to the NJU26101 up to the NJU26199.
The individual function is described in the each data sheet. Please refer to the
each data sheet to find the detail functions. The firmware commands are
described in the each firmware document.
■ Hardware Specification
NJU26100 Series
• 24bit Fixed-point Digital Signal Processing
• Maximum System Clock Frequency
: 38MHz
• Digital Audio Interface
: 3 Input ports / 3 Output ports
• Master / Slave Mode
• Master Mode MCK
:1/2 fclk, 1/3 fclk
ex. MCK = 384Fs(1/2) or MCK = 256Fs(1/3)
• Two kinds of micro computer interface
I2C bus (standard-mode/100kbps)
Serial interface (4 lines: clock, enable, input data, output data)
• Power Supply
: 2.5V ( 3.3V Input tolerant )
• Package
: QFP32-R1
at fclk=768Fs
AD1/SDIN AD2/SSb
NJU26100 Series
SCL/SCK
SDA/SDOUT
RESETb
MCK
XI
XO
SERIAL
HOST
INTERFACE
DSP ARITHMETIC UNIT
PROGRAM
CONTROL
ALU
24-BIT x 24-BIT
MULTIPLIER
TIMING
GENERATOR
ADDRESS GENERATION UNIT
SERIAL AUDIO
INTERFACE
SERIAL OUT
SERIAL OUT
SERIAL OUT
SERIAL IN
SERIAL IN
SERIAL IN
BCKO
LRO
SDO0
SDO1
SDO2
SDI0
SDI1
SDI2
BCKI
LRI
DELAY
RAM
DATA
RAM
FIRMWARE
ROM
GPIO AND
CONFIGURATION
INTERFACE
GPIO0
GPIO1
Ver.2005-02-24
-1-
1 page  
www.DataSheet4U.com
2. Clock and Reset
NJU26100 Series
The NJU26100 Series XI pin requires the system clock that should be related to the sample frequency Fs. The
XI/XO pins can generate the system clock by connecting the crystal oscillator or the ceramic resonator.
When the external oscillator is connected to XI/XO pins, check the voltage level of the pins. Because the
maximum input voltage level of XI pin is deferent from the other input or bi-directional pins. The maximum
voltage-level of XI pin equals to VDD.
To initialize the NJU26100 Series, RESETb pin should be set Low level during some period. After some period of
Low level, RESETb pin should be High level. This procedure starts the initialization of the NJU26100 Series.
To select I2C bus or 4-Wire serial bus, some level should be supplied to GPIO0 pin (SEL1 pin). When GPIO0 pin
(SEL1 pin)=”Low”, I2C bus is selected. When GPIO0 pin (SEL1 pin)=”High”, 4-Wire serial bus is selected. The level
of GPIO0 pin (SEL1 pin) is checked by the NJU26100 Series in 1 m sec after RESETb pin level goes to “High”.
After the power supply and the oscillation of the NJU26100 Series becomes stable, RESETb pin should be kept
Low-level more than tRESETb period.
VDD
XI
RESETb
OSC unstable
OSC stable
tRESETb
Fig. 2- 1 Reset Timing
Table 2- 1 Reset Time
Symbol
Time
tRESETb
≥1µs
Notice :
Please consult with manufacture of crystal oscillator / ceramic resonator enough in use of these parts.
NJRC would not take the responsibility on the external parts of clock generating.
Ver.2005-02-24
-5-
5 Page 
www.DataSheet4U.com
4.3 Serial Audio Timing
NJU26100 Series
Table 4-1 Serial Audio Input Timing Parameters (VDDO=VDDC=VDDR=2.5V, VSSO=VSSC=VSSR=0V, Ta=25°C)
Parameter
Symbol
Test Condition
Min Typ. Max Units
BCKI Frequency **
BCKI Period
**
Low Pulse Width
High Pulse Width
BCKI to LRI Time **
fBCKI
tSIL
tSIH
TSLI
0.9 - 4.0 MHz
85 -
85
40 -
- ns
- ns
LRI to BCKI Time **
tLSI
40 -
- ns
Data Setup Time *
tDS
40 -
- ns
Data Hold Time *
tDH
40 -
- ns
* It is the regulation to BCKI in slave mode and to BCKO in master mode.
** It is the regulation in slave mode.
LRI
BCKI
SDI0,1
tSIH tSIL tSLI tLSI
tDS tDH
Fig. 4-14 Serial Audio Input Timing
Ver.2005-02-24
- 11 -
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet NJU26100.PDF ] | |
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