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PDF DS50PCI401 Data sheet ( Hoja de datos )
| Número de pieza | DS50PCI401 | |
| Descripción | 2.5 Gbps / 5.0 Gbps 4 Lane PCI Express Transceiver | |
| Fabricantes | National Semiconductor Corporation | |
| Logotipo |  |
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DS50PCI401
June 25, 2009
2.5 Gbps / 5.0 Gbps 4 Lane PCI Express Transceiver with
Equalization and De-Emphasis
General Description
The DS50PCI401 is a low power, 4 lane bidirectional buffer/
equalizer designed specifically for PCI Express Gen1 and
Gen2 applications. The device performs both receive equal-
ization and transmit de-emphasis, allowing maximum flexibil-
ity of physical placement within a system. The receiver is
capable of opening an input eye that is completely closed due
to inter-symbol interference (ISI) induced by the interconnect
medium.
The transmitter de-emphasis level can be set by the user de-
pending on the distance from the DS50PCI401 to the PCI
Express endpoint. The DS50PCI401 contains PCI Express
specific functions such as Transmit Idle, RX Detection, and
Beacon signal pass through.
The device will change the load impedance on its input pins
based on the state of RXDETA/B inputs detection. An internal
rate detection circuit is included to detect if an incoming data
stream is at Gen2 data rates, and adjusts the de-emphasis
on it's output accordingly. The signal conditioning provided by
the device allows systems to upgrade from Gen1 data rates
to Gen2 without reducing their physical reach. This is true for
FR4 applications such as backplanes, as well as cable inter-
connect.
Features
■ Input and Output signal conditioning increases PCIe reach
in backplanes and cables
■ 0.09 UI of residual deterministic jitter at 5Gbps after 42” of
FR4 (with Input EQ)
■ 0.11 UI of residual deterministic jitter at 5Gbps after 7m of
PCIe Cable (with Input EQ)
■ 0.09 UI of residual deterministic jitter at 5Gbps with 28” of
FR4 (with Output DE)
■ 0.13 UI of residual deterministic jitter at 5Gbps with 7m of
PCIe Cable (with Output DE)
■ Adjustable Transmit VOD 800 to 1200mVp-p
■ Automatic power management on an individual lane basis
via SMBus
■ Adjustable electrical idle detect threshold.
■ Data rate optimized 3-stage equalization to 26 dB gain
■ Data rate optimized 6-level 0 to 12 dB transmit de-
emphasis
■ Flow-thru pinout in 10mmx5.5mm 54-pin leadless LLP
package
■ Single supply operation at 2.5V
■ >6kV HBM ESD rating
■ -10 to 85°C operating temperature range
Typical Application
© 2009 National Semiconductor Corporation 300604
30060480
www.national.com
1 page  
Pin Name
www.DatDaSEhMeAe0t4,UD.cEoMmA1
DEMB0, DEMB1
Pin Number
49, 50
53, 54
I/O, Type
I,FLOAT,
LVCMOS
Pin Description
DEMA/B ,0/1 controls the level of de-emphasis of the A/B
sides as shown in Table 2. The DEMA/B pins are only active
when ENSMB is de-asserted (Low). Each of the 4 A/B
channels have the same level unless controlled by the SMBus
control registers. When ENSMB goes High the SMBus
registers provide independent control of each lane and the
DEM pins are converted to SMBUS AD0/AD1 and SCL/SDA
inputs.
RATE
21
I,FLOAT,
RATE control pin controls the pulse width of de-emphasis of
LVCMOS
the output. A Low forces Gen1 (2.5Gbps), High forces Gen 2
(5Gbps), Open/Floating the rate is internally detected after
each exit from idle and the pulse width is set appropriately.
When ENSMBUS= 1 this pin is disabled and the RATE
function is controlled internally by the SMBUS registers. Refer
to Table 2.
Control Pins — Both Modes (LVCMOS)
RXDETA,RXDETB 22,23
I, LVCMOS w/ The RXDET pins in combination with the ENRXDET pin
internal
controls the receiver detect function. Depending on the input
pulldown
level, a 50Ω or >50KΩ termination to the power rail is enabled.
Refer to Table 5.
PRSNT
52 I, LVCMOS Cable Present Detect input. High when a cable is not present
per PCIe Cabling Spec. 1.0. Puts part into low power mode.
When low (normal operation) part is enabled.
ENRXDET
26
I, LVCMOS w/ Enables pin control of receiver detect function. Pin must be
internal
pulled high externally for RXDETA/B to function. Controls
pulldown
both A and B sides. Refer to Table 5.
TXIDLEA,TXIDLEB 24,25
I, FLOAT,
LVCMOS
Controls the electrical idle function on corresponding outputs
when enabled. H= electrical Idle, Float=autodetect (Idle on
input passed to output), L=Idle squelch disabled as shown in
Table 3.
Analog
SD_TH
27 I, ANALOG Threshold select pin for electrical idle detect threshold. Float
pin for default 130mV DIFF p-p, otherwise connect resistor
from SD_TH to GND to set threshold voltage as shown in
Table 4.
Power
VDD
9, 14,36, 41, Power
51
Power supply pins CML/analog.
GND
DAP
Power
Ground pad (DAP - die attach pad).
Notes:
FLOAT = 3rd input state, don't drive pin. Pin is internally biased to mid level with 50 kΩ pull-up/pull-down. If high Z
output not available, drive input to VDD/2 to assert mid level state.
Internal pulldown = Internal 30 kΩ pull-down resistor to GND is present on the input.
LVCMOS inputs without the “Float” conditions must be driven to a logic Low or High at all times or operation is not
guaranteed.
Input edge rate for LVCMOS/FLOAT inputs must be faster than 50 ns from 10–90%.
Functional Description
The DS50PCI401 is a low power media compensation 4 lane
transceiver optimized for PCI Express Gen 1 and Gen 2 me-
dia including lossy FR-4 printed circuit board backplanes and
balanced cables. The DS50PCI401 operates in two modes:
Pin Control Mode (ENSMB = 0) and SMBus Mode (ENSMB
= 1).
Pin Control Mode:
When in pin mode (ENSMB = 0) , the transceiver is config-
urable with external pins. Equalization and de-emphasis can
be selected via pin for each side independently. When de-
emphasis is asserted VOD is automatically increased per the
De-Emphasis table below for improved performance over
lossy media. The receiver detect pins RXDETA/B provide
manual control for input termination (50Ω or >50KΩ). Rate
optimization is also pin controllable, with pin selections for
2.5Gbps, 5Gbps, and auto detect. The receiver electrical idle
detect threshold is also programmable via an optional exter-
nal resistor on the SD_TH pin.
5 www.national.com
5 Page 
Symbol
VwTwXw-C.MD-DaCta- SLIhNeEe-DtE4LUT.Acom
TTX-IDLE-SET-TO -IDLE
TTX-IDLE-TO -DIFF-DATA
TPDEQ
TPD
TLSK
TPPSK
Parameter
Conditions
Absolute Delta of DC
Common Mode
Voltage between Tx+
and Tx-
Max time to transition to VIN = 800 mVp-p, 5 Gbps,
valid diff signaling after Figure 5
leaving Electrical Idle
Max time to transition to VIN = 800 mVp-p, 5 Gbps,
valid diff signaling after Figure 5
leaving Electrical Idle
Differential
Propagation Delay
EQ = 11,
+4.0 dB @ 2.5 GHz , Figure 4
(Note 9)
Differential
Propagation Delay
EQ = FF,
Equalizer Bypass, Figure 4
(Notes 9, 8)
Lane to Lane Skew in a TA = 25C,VDD = 2.5V
Single Part
(Notes 7, 8)
Part to Part
Propagation Delay
Skew
TA = 25C,VDD = 2.5V
Min
Typ Max
Units
25 mV
6.5 9.5
5.5 8
150 200 250
120 170 220
27
35
nS
nS
ps
ps
ps
ps
11 www.national.com
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet DS50PCI401.PDF ] | |
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