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PDF DS64BR401 Data sheet ( Hoja de datos )
| Número de pieza | DS64BR401 | |
| Descripción | Quad Bi-Directional Transceiver | |
| Fabricantes | National Semiconductor Corporation | |
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DS64BR401
June 25, 2009
Quad Bi-Directional Transceiver with Equalization and
De-Emphasis
General Description
The DS64BR401 is a quad lane bi-directional signal condi-
tioning transceiver suitable for 6.0/3.0/1.5 Gbps SATA/SAS
and other high-speed bus applications with data rates up to
6.4 Gbps. The device performs both receive equalization and
transmit de-emphasis on each of its 8 channels to compen-
sate for channel loss, allowing maximum flexibility of physical
placement within a system. The receiver's continuous time
linear equalizer (CTLE) provides a boost of up to +33 dB at 3
GHz and is capable of opening an input eye that is completely
closed due to inter-symbol interference (ISI) induced by the
interconnect medium. The transmitter features a pro-
grammable output de-emphasis driver and allows amplitude
voltage levels to be selected from 600 mVp-p to 1200 mVp-p
to suit multiple application scenarios. This Low Power Differ-
ential Signaling (LPDS) output driver is a power efficient
implementation that maintains compatibility with AC coupled
CML receiver. The programmable settings can be applied via
pin settings or SMBus interface.
To enable seamless upgrade from SAS/SATA 3.0 Gbps to 6.0
Gbps data rates without compromising physical reach,
DS64BR401 automatically detects the incoming data rate and
selects the optimal de-emphasis pulse width. The device de-
tects the out-of-band (OOB) idle and active signals of the
SAS/SATA specification and passes through with minimum
signal distortion.
With a typical power consumption of 200 mW/lane (100 mW/
channel) at 6.4 Gbps, and control to turn-off unused channels,
the DS64BR401 is part of National's PowerWise family of en-
ergy efficient devices.
Features
■ Quad lane bi-directional transceiver up to 6.4 Gbps rate
■ Signal conditioning on input and output for extended reach
■ Adjustable receive equalization up to +33 dB gain
■ Adjustable transmit de-emphasis up to −12 dB
■ Adjustable transmit VOD (600 mVp-p to 1200 mVp-p)
■ <0.25 UI of residual DJ at 6.4 Gbps with 40” FR4 trace
■ Automatic de-emphasis scaling based on rate detect
■ SATA/SAS: OOB signal pass-through,
<3 ns (typ) envelope distortion
■ Adjustable electrical IDLE detect threshold
■ Low power (100 mW/channel), per-channel power down
■ Programmable via pin selection or SMBus interface
■ Single supply operation at 2.5V ±5%
■ >6 kV HBM ESD Rating
■ 3.3V LVCMOS input tolerant for SMBus interface
■ High speed signal flow–thru pinout package: 54-pin LLP
(10 mm x 5.5 mm)
Applications
■ SATA (1.5, 3.0 and 6 Gbps)
■ SAS (1.5, 3.0 and 6 Gbps)
■ XAUI (3.125 Gbps), RXAUI (6.25 Gbps)
■ sRIO – Serial Rapid I/O
■ Fibre Channel (4.25 Gbps)
■ 10GBase-CX4, InfiniBand 4x (SDR & DDR)
■ QSFP active copper cable modules
■ High-speed active cable and FR-4 backplane traces
Typical Cable Application
© 2009 National Semiconductor Corporation 300730
30073081
www.national.com
1 page  
Pin Name
Pin Number I/O, Type
www.DatCaSohnetreot4l UP.icnosm— Both Modes (LVCMOS)
Pin Descriptions
RATE
21
I, Float,
RATE, 3–level controls the pulse width of de-emphasis of the
LVCMOS
output.
RATE = 0 forces 3 Gbps,
RATE = 1 forces 6 Gbps,
RATE = Float enables auto rate detection and the pulse width
(pull-back) is set appropriately after each exit from IDLE. This
requires the transition from IDLE to ACTIVE state — OOB
signal. See Table 2
TXIDLEA,TXIDLEB 24, 25
I, Float,
LVCMOS
TXIDLEA/B, 3–level controls the driver output.
TXIDLEA/B = 0 disables the signal detect/squelch function for
all A/B outputs.
TXIDLEA/B = 1 forces the outputs to be muted (electrical idle).
TXIDLEA/B = Float enables the signal auto detect/squelch
function and the signal detect voltage threshold level can be
adjusted using the SD_TH pin. See Table 3
VOD0, VOD1
22, 23
I, LVCMOS w/ VOD[1:0] adjusts the output differential amplitude voltage
internal pull- level.
down
VOD[1:0] = 00 sets output VOD = 600 mV (Default)
VOD[1:0] = 01 sets output VOD = 800 mV
VOD[1:0] = 10 sets output VOD = 1000 mV
VOD[1:0] = 11 sets output VOD = 1200 mV
PWDN
52 I, LVCMOS PWDN = 0 enables the device (normal operation).
PWDN = 1 disables the device (low power mode).
Pin must be driven to a logic low at all time or normal operation
is not guaranteed.
Analog
SD_TH
27 I, ANALOG Threshold select pin for electrical idle detect threshold. Float
pin for typical default 130 mVp-p (differential), otherwise
connect resistor from SD_TH to GND to set threshold voltage.
See Table 4, Figure 5
Power
VDD
9, 14, 36, 41, Power
51
Power supply pins. 2.5 V +/-5%
GND
DAP
Power
DAP is the large metal contact at the bottom side, located at
the center of the 54 pin LLP package. It should be connected
to the GND plane with at least 4 via to lower the ground
impedance and improve the thermal performance of the
package.
NC 26
No Connect — Leave pin open
1 = HIGH, 0 = LOW, FLOAT = 3rd input state.
Don't drive FLOAT pin; pin is internally biased to mid level with 50 kΩ pull-up/pull-down.
Internal pulled-down = Internal 30 kΩ pull-down resistor to GND is present on the input.
Input edge rate for LVCMOS/FLOAT inputs must be faster than 50 ns from 10–90%.
5 www.national.com
5 Page 
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FIGURE 1. LPDS Output Transition Times
300730502
300730503
FIGURE 2. Propagation Delay Timing Diagram
FIGURE 3. Idle Timing Diagram
300730504
FIGURE 4. SMBus Timing Parameters
11
30073094
www.national.com
11 Page | ||
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| PDF Descargar | [ Datasheet DS64BR401.PDF ] | |
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